Substrate-less microelectronic package

Details Substrate-less microelectronic package Substrate-less microelectronic package

2003-04-22

2004-09-21

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Insulating material

C257S777000

Reexamination Certificate

active

06794748

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to apparatus and methods for fabricating microelectronic packages. In particular, the present invention relates to low profile microelectronic packages, which are fabricated without a substrate.
2. State of the Art
Higher performance, reduced cost, increased miniaturization of integrated circuit components, and greater packaging densities of microelectronic devices are ongoing goals of the microelectronics industry. One method of increasing the density of microelectronic device packages is to stack the individual microelectronic dice within the packages. Furthermore, low-profile (thin) microelectronic packages are in high demand for use in small electronic devices, such as cell phones. Thus, the microelectronics industry fabricates a variety of thin, stacked packages.
FIG. 8
illustrates one such package known as an Ultra Thin Molded Matrix Array Package (UTMMAP). The UTMMAP
200
comprises a first microelectronic die
202
(such as a microprocessor, a chipset, a memory device, an ASIC, and the like) attached by its back surface
204
to a first surface
206
of a carrier substrate
208
(such as an interposer, a motherboard, a back surface of another microelectronic die, or the like). A first plurality of bond wires
212
extend from bond pads (not shown) on an active surface
214
of the first microelectronic die
202
to land pads (not shown) on the carrier substrate first surface
206
to make electrical contact therebetween, as will be understood by those skilled in the art. A second microelectronic die
216
is stacked by its back surface
218
on the first microelectronic die
202
with an appropriately sized spacing device
220
disposed therebetween to allow clearance for the first bond wires
212
. The second microelectronic die
216
makes electrical contact with the carrier substrate
208
through a second plurality of bond wires
222
extending between bond pads (not shown) on an active surface
224
of the second microelectronic die
216
and land pads (not shown) on the carrier substrate
208
. The stacked microelectronic dice are then encapsulated with a molding compound
226
. The carrier substrate
208
also includes a plurality of external contacts
228
attached to a second surface
232
thereof. These external contacts
228
are used to connect the package to an external component (no shown), as will be understood to those skilled in the art.
Another thin, stacked package configuration is known as a Foiled Flex Ball Grid Array (FF-BGA). Such a package includes the use of a flexible substrate to route electrical traces from the second microelectronic dice stack to a position between the first microelectronic dice stack and the carrier substrate to make electrical contact therewith.
FIG. 9
shows such an FFBGA package
240
, wherein a first microelectronic dice stack
242
and a second microelectronic dice stack
244
are attached to and in electrical contact with a first surface
248
of a flexible substrate
246
through wire bonds
252
and
254
, respectively. The first microelectronic dice stack
242
and second microelectronic dice stack
244
may be fabricated in a manner discussed above with regard to the UTMMAP
200
of
FIG. 8. A
molding compound
256
,
258
is dispersed proximate each of the first microelectronic dice stack
242
and the second microelectronic dice stack
244
, respectively.
The flexible substrate
246
includes conductive traces (not shown) disposed therein, thereon, and/or therethrough, which make contact with an array
264
of external interconnects
266
(such as solder balls) disposed on a second surface
262
of the flexible substrate
246
proximate the first microelectronic dice stack
242
. Thus, both the first microelectronic dice stack
242
and the second microelectronic die stack
244
have external interconnects
266
within the array
264
. The flexible substrate
246
is bent such that a back surface
272
of the first microelectronic dice stack
242
can be attached to a back surface
274
of the second microelectronic dice stack
244
with a layer of adhesive
276
. The external interconnects
266
are attached to a substrate
278
using a C4 (controlled collapse chip connect) process.
Although such approaches result in effective thin, stacked packages, these packages have poor thermal performance (i.e., do not dissipate heat well from the microelectronic dice therein) due to the poor thermal conductivity of the molding compound and carrier substrates used by these packages. Therefore, it would be advantageous to develop a thin, stacked package that is capable of effective thermal dissipation.


REFERENCES:
patent: 5910682 (1999-06-01), Song
patent: 6265771 (2001-07-01), Ference et al.
patent: 6339254 (2002-01-01), Venkateshwaran et al.
patent: 6665187 (2003-12-01), Alcoe et al.

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