Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-06-30
2004-04-06
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185200, C365S185250
Reexamination Certificate
active
06717856
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention generally relates to memory technology and more specifically relates to sense amplifiers in FLASH memory devices.
2. Description of the Related Art
Most memory technology employs sense amplifiers. These sense amplifiers are typically designed for low current inputs with high gain and rapid response times. However, memory technology also often involves selecting a particular cell and letting that cell pull a node down or up, to a different value from what the node is biased to when no cell is selected. That node is typically the input node of the sense amplifier. As a result, the fastest sense amplifier is of little use if the input node can only be pulled to a different voltage slowly by the memory cell.
One method for providing a memory cell that can rapidly pull a node up or down is to use a large transistor in the memory cell, thus allowing for high current which may pull the node to the desired voltage. However, the larger the transistor, the more space the memory cell requires, and therefore the lower the density of memory cells can be on a given memory chip. Furthermore, a larger transistor may have increased capacitive coupling effects which will lead to a slower transition from a non-conductive to a conductive state, resulting in a property of the larger transistor defeating the purpose of having the larger transistor.
Beyond problems with how quickly a node may be pulled down or up, problems may arise when comparing a reference cell and memory cell response due to settling time on the inputs to the sense amplifier. If the reference cell has a greater effect on the reference input node initially than the memory cell has on the sense input node, then the sense amplifier may generate a signal which is false early in the cycle, before the sense input node transitions properly. This means that the delay associated with the sense amplifier may be longer than would otherwise be expected or preferable.
REFERENCES:
patent: 4884241 (1989-11-01), Tanaka et al.
patent: 5305273 (1994-04-01), Jinbo
patent: 5519652 (1996-05-01), Kumakura et al.
patent: 5559737 (1996-09-01), Tanaka et al.
patent: 5594691 (1997-01-01), Bashir
patent: 6307797 (2001-10-01), Fournel et al.
Guliani Sandeep
Srinivasan Balaji
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Mai Son
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