Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2002-02-25
2004-05-11
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S633000, C438S693000
Reexamination Certificate
active
06734103
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a polishing or grinding technique for planarizing the surface of a substrate and, more in particular, it relates to a method and an apparatus for manufacturing semiconductor integrated circuits in which thin films formed on semiconductor substrates are subjected to polishing or grinding.
In recent years, a planarizing technique has become important for shallow trench isolation, and formation of tungsten plugs and formation of wiring layers for transmission of signals from each of transistor elements to wiring layers in the manufacture of semiconductor integrated circuits. For the planarization, a polishing technique referred to as chemical mechanical polishing (CMP) is typical.
In particular, copper has been used recently for wiring materials. A damascene method is predominant in the planarization, which is disclosed in, for example, Japanese Patent Laid-Open Hei 2-278822 and Japanese Patent Laid-Open Hei 8-83780.
When copper is used as a wiring material, it can provide a merit in view of durability and lowering of resistance value as compared with existent aluminum wirings but, on the contrary, it requires consideration for insulation failure caused by conductive ions such as diffusion into oxide films. In the damascene method, as shown in
FIG. 2
, diffusion is prevented by depositing a barrier film
14
at the boundary between an oxide film
13
and copper
15
as the wiring material. By the presence of the barrier film
14
, copper
15
is buried into trenches by way of the steps from
FIG. 2I
to in FIG.
2
III by the damascene method.
In the formation of the copper wirings by the damascene method, control of the processing speed for the copper
14
and the barrier film
14
is important. Generally, since the processing speed for the barrier film (mainly Ta, TaN) is lower as compared with that for copper, copper is ground excessively when processing is continuously applied from
FIG. 2I
to in FIG.
2
III all at once. In view of the above, plural kinds of slurries are provided separately, such as a slurry for polishing copper at a high speed, a slurry for polishing the barrier film at a high speed while polishing copper at a low speed, or a slurry capable of polishing copper, barrier film and oxide film at an equal speed. The actual CMP step adopts a method of conducting the step I by using a slurry of polishing copper at a high speed and then conducting the step in FIG.
2
II by applying a slurry capable of polishing a barrier film while changing a polishing disk. As the case may be, it sometimes use a slurry capable of processing copper, barrier film and oxide film at an identical speed as the third step CMP, thereby improving the planarity and reducing scratches.
Another prior art technique includes a method of using fixed abrasive grains for the planarization of copper. A sheet in which alumina abrasives are fixed with a resin is used and it has a feature of not requiring a slurry containing free abrasives. However, the method still requires CMP at 2 to 3 steps for removing the barrier film
14
. This technique is described in the proceedings: “2000 Chemical Mechanical Planarization for ULSI Multilevel Interconnection Conference”, in pp. 58-65.
Further, as other prior art using fixed abrasive tool, an example is described in U.S. Pat. No. 5,972,792. This is a method of planarization while preventing etching to a workpiece by controlling pH of a processing solution. This technique also belongs to a multistep planarization method of changing the polishing method on every workpiece for each layer using the fixed abrasive tool.
In a case of practicing planarization of the damascene method described above using CMP, there are several problems. One of them is attributable to that Ta or TaN used for the barrier film
14
is harder than copper, so that two or more steps of CMP have to be applied while separately conducting CMP for copper
15
and the barrier film
14
, which results in increased cost, lowering of throughput and increase in the environmental load due to increase of waste slurry.
As another problem, since the polishing pad is soft, dishing and erosion which forms recesses on the surface of wirings as shown in
FIG. 4
are produced and, as a result, variation for the value of the wiring resistance increases. In particular, this gives a significant problem in a logic device called as a system LSI having a multi-layered wiring structure as shown in FIG.
7
. That is, when the planarity of the lower layer is low as shown in
FIG. 6
, it impairs the planarity beyond the performance of CMP to cause a fatal defect that short circuit or disconnection tends to occur between wirings by polishing residue. This is described in “New Material and Process Technology for Next Generation ULSI Multi-layered wirings”, by technical information society, in pp. 242-246.
This invention intends to provide a method and an apparatus for manufacturing a semiconductor device with improved throughput by constituting CMP steps with a single step in order to overcome the foregoing problems.
This invention further intends to provide a manufacturing method of a semiconductor device for improving the yield including the reduction of variation of the wiring resistance value and reduction of the disconnection failure by reducing dishing and erosion.
SUMMARY OF THE INVENTION
To attain the foregoing object, this invention provides a method for manufacturing a semiconductor device wherein for a substrate as a workpiece in which an insulation film is formed to the substrate, openings are formed in the insulation film, a first conductive film (for example, a barrier film) is formed in the inside of the openings and on the surface of the insulation film, and a second conductive film (for example, a copper film) is formed on the first conductive film, by planarizing the second conductive film and part of the first conductive film using a fixed abrasive tool, the first and the second planarized conductive film are formed in the openings, said method comprising: supplying a first processing liquid upon planarization of the second conductive film and switching the supply of the liquid from the first processing liquid to the second processing liquid upon planarization of the second and the first conductive film.
Further, this invention provides A method for manufacturing a semiconductor device wherein for a substrate as a workpiece in which an insulation film is formed to the substrate, openings are formed in the insulation film, a first conductive film (for example, a copper film) is formed in the inside of the openings and on the surface of the insulation film, and a second conductive film (for example, a copper film) is formed on the first conductive film, by planarizing the second conductive film and part of the first conductive film using a fixed abrasive tool, the first and the second planarized conductive film are formed in the openings, said method comprising: dressing the surface of the fixed abrasive tool before planarization of the second and the first conductive film.
Further, this invention provides a method of manufacturing a semiconductor device as described above, wherein the distance of the insulative film between adjacent openings is within a range of 30 &mgr;m to 0.1 &mgr;m, and dishing and erosion on the planarized surface is 40 nm or less.
Further, this invention provides a method of manufacturing a semiconductor device as described above, wherein each of the first and the second processing liquids contains an oxidizing agent, an organic acid, a corrosion inhibitor and purified water.
Further, this invention provides a method of manufacturing a semiconductor device as described above, wherein each of the first and the second processing liquids contain aqueous hydrogen peroxide, malic acid, benzotriazole and purified water.
Further, this invention provides a method manufacturing a semiconductor device as described above, wherein each of the first and the second processing liquid contains from 0.5 to 50% of aqueous hydrogen peroxide,
Katagiri Souichi
Kawamura Yoshio
Kondo Seiichi
Yamaguchi Ui
Yasui Kan
A. Marquez, Esq. Juan Carlos
Fisher Esq. Stanley P.
Hitachi , Ltd.
Niebling John F.
Reed Smith LLP
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