Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2002-01-17
2004-09-21
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S748000
Reexamination Certificate
active
06794754
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the present invention relates to a semiconductor device using a porous semiconductor oxide film as an interlayer insulating film and a method of manufacturing the same.
2. Description of the Related Art
Recently, a design rule has been shortened to 0.25 &mgr;m or less in a semiconductor device such as a microprocessor. For this reason, severe problems occur in a process of manufacturing the semiconductor device having such a finer design rule. The problems cannot be solved by a conventional manufacturing technique. For example, one of the problems is a delay due to R×C, where R is a wiring resistance and C is a wiring capacitance. This problem becomes an obstacle to an improvement in a LSI performance based on a high speed operation of transistors. Unless any a counter-plan is carried out, Moore's law can not be maintained.
A technique to increase an operational frequency of an LSI is clear in the manufacturing process of an LSI having 0.25-&mgr;m design rule. It is enough to miniaturize the transistor and then shorten the length of a gate. Thus, a switching speed of the transistor can be increased. However, recently, this method cannot be applied any longer. Increase of the switching speed of the transistor contributes only a little to the improvement of the operation speed of the LSI. This is because most of processors have critical paths through which signals are transmitted from an end of the LSI to another end thereof. Thus, the delay due to the time constant RC in a wiring pattern largely contributes to the operation speed of the LSI. Typically, reduction of a design rule makes the operational frequency higher. This is because the maximum length of a signal transmission path becomes shorter. However, when it is intended to produce a new LSI having a size larger than that of the conventional LSI by a new manufacturing process, it becomes difficult to improve the operational frequency of the new LSI.
The metal wiring patterns in such an LSI are roughly classified into a very fine wiring pattern group, a slightly thick wiring pattern group and a bus line. The very fine wiring pattern group is referred to as local wiring patterns through which a data within a function block is transmitted. The slightly thick wiring pattern group is referred to as global wiring patterns, through which a clock signal and power are supplied to the function block. The bus line is used to transmit data between the function blocks. These wiring patterns are generally formed on an insulating layers referred to as an interlayer insulating film.
Now, a width and thickness of the local wiring pattern used for the most advanced LSI having the design rule of 0.18 &mgr;m is approximately 0.2 &mgr;m. Such local wiring patterns are laid in the same interval of 0.2 &mgr;m. On the other hand, the global wiring pattern has various widths from 5 to 100 &mgr;m. Multi-layer metal wiring patterns are electrically connected through metals such as tungsten (W) embedded in fine holes referred to as a via hole or a through hole and formed in an interlayer insulating film.
These metal wiring patterns are further made finer for an LSI with the design rule of 0.1 &mgr;m. A problem in making the multi-layer wiring pattern fine is the increase of the RC delay due to increase of the wiring resistance of a global wiring pattern. The wiring resistance increases with increase of the chip size of the LSI, and an inter-pattern capacitance increases due to the reduction of a gap between the local wiring patterns.
As a method of reducing the wiring pattern resistance R, it is enough to select a wiring pattern material having a smaller resistivity. For example, it is considered to use Cu or Au instead of Al that has been used up to now, and it is actually used in a partial field. Although Cu is a material having a very small resistance so that Cu is effective in reducing the wiring pattern resistance, it is easy to be diffused into Si. Thus, a barrier layer is needed on the surface of a silicon film. Although Au has a small resistance, it requires the barrier layer similarly to Cu. Therefore, Au does not have an advantage over Cu.
Reduction of the wiring pattern capacitance C is possible by replacing a SiO
2
film with a low dielectric material such as a fluorine doped SiO
2
or an organic insulating film. The fluorine doped SiO
2
film has a dielectric constant lower than that of SiO
2
. However, the fluorine doped SiO
2
film would be still high in a dielectric constant in future. Also, the organic insulating film lacks in the stableness at a high temperature and the wiring pattern material diffuses into the organic insulating film. Although the most excellent dielectric substance is vacuum, it is the atmosphere in view of the practical use. The relative dielectric constant thereof is substantially equal to “1”.
The technique referred to as an air bridge is known in which all the dielectric films are removed to float a wiring pattern in the space. However, it requires a number of poles such that a resonance frequency of the wiring pattern extremely exceeds a signal frequency used in the chip so as to support and protect the wiring pattern and protect against destruction resulting from a vibration. Although this method is already successful, it results in a high manufacturing cost. Therefore, it will be a long time before this method is actually used.
The reason of the increase of RC product due to the change of the design rule will be described below. Although an actual LSI has the five to six wiring pattern layers, the case of the two layers will be considered below in order to simplify the analysis.
The important dimension in the wiring pattern is a wiring pattern pitch, which determines the shortest distance between the wiring patterns and the minimum size of the chip. A usual wiring pattern pitch is approximately two times the width of the wiring pattern. The change from the manufacturing process for a 0.5-&mgr;m wiring pattern to that for a 0.25-&mgr;m wiring pattern reduces the wiring pattern width W to a half. Since an area of the chip is proportional to the square of W at this time, the area of the chip is reduced to the quarter.
On the other hand, the resistance of the metal wiring pattern is inversely proportional to a sectional area (TW). The increase of the resistance leads to the main cause of the delay. Unavoidably, the resistance must be reduced by maintaining the thickness T of a metal pattern or making it thicker. However, the increase of the film thickness of the wiring pattern increases a capacitance between the wiring patterns in a horizontal direction. This is because an area of portions opposite to and parallel to each other is increased irrespective of the reduction of the width between the metal wiring patterns.
As mentioned above, the increase of the capacitance and the increase of the resistance are in the relation of trade-off. Therefore, the approach of suppression of the RC product from the wiring pattern design reaches its limit.
Now, the material used for an interlayer insulating film is SiO
2
, and the relative dielectric constant thereof is approximately 4.0. This value is still high. Thus, it is said that SiO
2
could be used until the present generation of 0.25 &mgr;m at the most. Therefore, various materials other than fluorine doped SiO
2
are studied to reduce the dielectric constant.
SiOF has merit in that the conventional process can be substantially directly used, and is put to a practical use in a partial field. It can be manufactured by using a PE-CVD (Plasma Enhanced Chemical Vapor Deposition) method, similarly to SiO
2
. As a material gas, C
2
F
6
is used in addition to the SiO
2
material gas such as TEOS (Tetraethoxysilane; Si (OC
2
H
5
)
4
). It is reported that a vast addition of the fluorine reduces an ∈ value to about 2.7. However, the moisture absorption is increased in conjunction with the inc
Morisaki Hiroshi
Nozaki Shinji
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