Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2001-09-26
2004-04-27
Mengistu, Amare (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S100000
Reexamination Certificate
active
06727880
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a liquid crystal display (LCD) device and, more specifically, to a source driver capable of the reducing power consumption of a LCD device and a method for driving the LCD device with the source driver thereof.
BACKGROUND OF THE INVENTION
LCD devices have typically been used as display components in portable electronic apparatuses such as cellular phones and portable gaming devices. As power dissipated by a LCD device is most dominant in whole power consumption in a portable apparatus, battery life is shortened. The problem of insufficient battery power becomes more severe in a smaller sized portable apparatus, such as a miniature gaming device.
FIG. 1
shows a functional constitution of a known source driver employed in a LCD device, being associated with 240 channels. The source driver shown in
FIG. 1
has a register block
100
storing digital data signals, a level shifter
200
converting voltage levels of the digital data signals supplied from the register block
100
into predetermined voltage levels, a digital-to-analog converter (DAC)
300
generating an alternative one of a plurality of gradation voltages V
1
~V
64
in response to output signals from the level shifter
200
, and an output buffer
400
transferring output signals of the DAC converter
300
to source lines arranged in a LCD panel.
The register block
100
, which may be constructed in various architectures, includes a shift register
110
, a sampling register
120
, and a hold register
130
. The shift register
110
generates enable signals E
1
~Em in sequence. The sampling register
120
receives and stores the digital data signals that are R/G/B data signals R
0
~R
5
, G
0
~G
5
, and B
0
~B
5
in pixels, each of which is composed of three channels, in response to the enable signals E
1
~Em provided from the shift register
110
. The hold register
130
receives and stores the R/G/B data signals held in the sampling register
120
in pixels thereof in a time and transfers them to the level shifter
200
in response to a load signal LD.
With respect to operation of the source driver shown in
FIG. 1
, the sampling register
120
stores predetermined data bits, e.g., the R/G/B data signals R
0
~R
5
, G
0
~G
5
, and B
0
~B
5
, in response to the plurality of enable signals E
1
~Em supplied from the shift register
110
. For instance, when the first enable signal E
1
is applied to the shift register
110
, the sampling register
120
receives the first R/G/B signal and then simultaneously stores it into the first through third channels among plural channels. Consequently, the second R/G/B signal is simultaneously stored in the fourth through sixth channels among the plural channels in response to the second enable signal E
2
. Through the aforementioned procedures, all the R/G/B signals are settled in channels corresponding to pixels of the sampling register
120
in response to enable signals supplied from the shift register
110
. The R/G/B signals held in channels of the sampling register
120
move into channels of pixels in the hold register
130
in response to the externally supplied load signal LD.
The R/G/B signals divisionally assigned to channels are transferred to the level shifter
200
so as to be converted to signals having predetermined voltage levels. The level shifter
200
converts voltage levels of the R/G/B signals into predetermined levels before providing them to the DAC
300
which is driven at a high voltage.
The R/G/B signals with the converted voltage levels set by the level shifter
200
are applied to the DAC
300
. The DAC
300
selects an alternative one of the plurality of gradation voltages V
1
~V
64
in accordance with the output signals from the level shifter
200
and then provides such voltage to the output buffer
400
. The output buffer
400
applies analog signals generated from the DAC
300
to source lines arranged in the LCD panel (not shown).
In the construction of the source driver that is divided into the digital parts of registers and analog parts of the level shifters, the DAC and output buffer, the analog parts dissipate a large portion of the entire amount of power consumed by the source driver. In particular, most of the consumed power in the analog part is concentrated on the output buffer directly involved in a data output operation of the source driver. Current consumed by the buffer is classified as static current for a stand-by state, and operational current for normal activation. The current state that is dominant in the buffer is the static current because the operational current flows only for a very short time.
Considering current consumption properties in the buffer, the conventional manner for operating the source driver requires an increase in the number of buffers in proportion to the larger size and higher resolution of LCD panels desired by consumers, which magnifies the amount of power consumed. Furthermore, in the circumstance that LCD devices associated with the conventional source drivers are employed in miniaturized and portable electronic apparatuses such as cellular phones and gaming devices, problems are encountered when attempts are made to reduce power consumption, achieve a low power condition with batteries, or lengthen the operational life of batteries.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a source driver capable of reducing power consumption in a LCD device and to provide a method for driving the LCD device.
It is another object of the present invention to provide a source driver capable of reducing power consumption during a stand-by state in a LCD device and to provide a method for driving the LCD device.
In order to attain the above objects, according to an aspect of the present invention, there is provided a source driver of a liquid crystal display device, the source driver including a register block for storing digital data signals associated with tone information; a level shifter for converting voltage levels of the digital data signals into predetermined voltage levels; an output buffer controller for generating a plurality of buffer control signals in response to the digital data signals; a resistor string for establishing a plurality of gradation voltages with analog constituent; an output buffer for transferring the gradation voltages in response to the buffer control signals; and a digital-to-analog converter for providing the gradation voltages transferred from the output buffer into a liquid crystal display panel in response to output signals supplied from the level shifter.
According to another aspect of the invention, a source driver of a liquid crystal display device includes a shift register for generating a plurality of enable signals in sequence; a sampling register for storing a plurality of R/G/B data signals at their corresponding pixels in response to the enable signals; a hold register for storing the R/G/B data signals supplied through the sampling register; a level shifter for converting voltage levels of the R/G/B data signals of the hold register into predetermined voltage levels; an output buffer controller for generating a plurality of buffer control signals in response to the R/G/B data signals; a resistor string for establishing a plurality of gradation voltages with analog constituent; an output buffer for transferring the gradation voltages in response to the buffer control signals; and a digital-to-analog converter for providing the gradation voltages transferred from the output buffer into a liquid crystal display panel in response to output signals supplied from the level shifter.
The invention also provides a method for driving a liquid crystal display device having a plurality of buffer units and a liquid crystal display panel, the method including steps of generating a digital data signal as tone information; level-shifting the digital data signal; comparing the digital data signal with an address signal assigned to one of the buffer units; loading an alternative one o
Hynix / Semiconductor Inc.
Mengistu Amare
LandOfFree
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