Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2002-11-05
2004-04-06
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185110
Reexamination Certificate
active
06717849
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a flash memory device. More particularly, the invention relates to a flash memory device having a capacitor in which an erase switch is connected to each of word lines of one flash memory cell array and the other flash memory cell array is connected to a common terminal of the erase switch, thus reducing the manufacturing cost of a product without increasing a chip size while using a self-converged erase mode.
2. Description of the Prior Art
A flash memory cell being a non-volatile memory device, which can be electrically programmed and erased, is a semiconductor device used in portable electronic products such as notebook computers, PDAs, cellular phones, etc. and computer BIOS, printer, etc. In this flash memory cell, the threshold voltage of the cell is varied as electrons are moved due to a strong electric field to a thin tunnel oxide film of about 100 Å, so that program and erase operations are performed.
A general flash memory cell includes a stack gate in which a tunnel oxide film
12
, a floating gate
13
, a dielectric film
14
and a control gate
15
are sequentially stacked on a given region of a semiconductor substrate
11
; and a source
16
and a drain
17
both of which are formed at given regions of the semiconductor substrate
11
, as shown in FIG.
1
. At this time, the tunnel oxide film
12
is formed in thickness of about 100 Å. The floating gate
13
for storing electric charges is made of a polysilicon film. Also, the dielectric film
14
has a stack structure of a lower oxide film, a nitride film and an upper oxide film so that it has a high dielectric constant. Further, the control gate
15
that serves as a word line of the cell is made of a polysilicon film.
In the flash memory cell constructed above, a programming operation is performed in which channel hot electrons, which are generated by application of a high voltage of about 9V to the control gate and a voltage of about 5V having a pulse of 5 &mgr;sec to the drain with the source and semiconductor substrate grounded, pass over the potential barrier of the tunnel oxide film and are then stored at the floating gate. An erase operation is performed in which electrons stored at the floating gate are drawn out by means of FN tunneling by applying a negative high voltage of about −8V to the control gate and a high voltage of about 8V to the semiconductor substrate.
In this stack-type flash memory cell, when the erase operation is performed, there is a problem that the degree of erase between cells is varied due to defects in the manufacturing process or oxidization at an edge of the tunnel oxide film, or the like. Further, there is a problem that distribution of the cells is bad due to generation of over-erased cell since erase is not self-limited by tunneling.
In order to solve the problems due to the over-erased cell, adequate capacitor is connected within the flash memory cell array, as shown in FIG.
2
. In other words, as shown in
FIG. 2
, a plurality of PMOS transistors as a plurality of switching means that are driven by a given bias are connected to each of bit lines B/L. Also, a capacitor is connected between the plurality of the PMOS transistors and the ground terminal Vss. With this structure, it is possible to solve an over-erase problem by means of a soft program of a self-converged mode using the hot electrons that are generated in a diode reverse bias state between the drain and a bulk after the cells are erased. In this mode, however, it was found that the capacitance required to erase 1 sector (0.5M bits) is about 100 through 300 pF. In case that the capacitance of 100 through 300 pF is generated by a gate oxide film only, it was found that an area of 300 through 1000 &mgr;m
2
is required. In other words, the conventional method could solve distribution of the cell but require lots of chip size.
SUMMARY OF THE INVENTION
The present invention is contrived to solve the above problems and an object of the present invention is to provide a flash memory device capable of improving an erase mode and preventing power consumption by improving distribution of cells without increasing the chip size compared to addition of conventional capacitor, in a way that one flash memory cell array serving as a capacitor is connected to a drain of the other flash memory cell array in order to generate a soft program of a self-converged mode.
As described above, according to the prior art, if adequate capacitor is connected within the flash memory cell array, it was found that an over-erase problem could be solved by means of a soft program of a self-converged mode using hot electrons that are generated in a diode reverse bias state between a drain and a bulk after the cells are erased. At this time, however, the chip size is increased in order to implement the capacitor. On the contrary, according to the present invention, one flash memory cell array used as capacitor is connected to a drain of the other flash memory cell array. Due to this structure, a soft program of a self-converged mode can be used without increasing the chip size.
In order to accomplish the above object, a flash memory device according to the present invention, is characterized in that it comprises a first memory cell array having a plurality of first flash memory cells of which a gate of each cell of the plurality of first flash memory cells being connected to a respective first word line and a terminal of each cell of the plurality of first flash memory cells being connected to a respective first bit line; a plurality of switching means each having first and second terminals, the first terminal of each switching means being connected to the respective first bit line; and a second flash memory cell array having a plurality of second flash memory cells of which a gate of each cell of the plurality of second flash memory cells being connected to a common second word line and a terminal of each cell of the plurality of second flash memory cells being connected to a respective second bit liner wherein the second terminals of the plurality of the switching means are commonly connected to the common second word line.
REFERENCES:
patent: 5023837 (1991-06-01), Schreck et al.
patent: 5295113 (1994-03-01), Dix et al.
patent: 6091632 (2000-07-01), Yoshimi et al.
patent: 6104636 (2000-08-01), Tada
patent: 6256228 (2001-07-01), Hirano
patent: 6404681 (2002-06-01), Hirano
patent: 6504765 (2003-01-01), Joo
Hynix / Semiconductor Inc.
Phan Trong
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