Reference wafer and process for manufacturing same

Details Reference wafer and process for manufacturing same Reference wafer and process for manufacturing same

2001-12-07

2004-03-02

Young, Christopher G. (Department: 1756)

Radiation imagery chemistry: process, composition, or product th

Registration or layout process other than color proofing

C430S030000

Reexamination Certificate

active

06699627

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to processes for semiconductor manufacture and more particularly to semiconductor pattern overlay.
2. Description of Related Art
Lithographic processing is increasingly requiring ever tighter layer-to-layer overlay tolerances to meet device performance requirements. Overlay registration on critical layers can directly impact device performance, yield and repeatability. Increasing device densities, decreasing device feature sizes and greater overall device size conspire to make pattern overlay one of the most important performance issues during the semiconductor manufacturing process. The ability to accurately determine correctable and uncorrectable pattern placement error depends on fundamental techniques and algorithms used to calculate lens distortion, stage error, and reticle error.
Overlay registration generally refers to translational error that exists between features exposed layer to layer in a vertical fabrication process of semiconductor devices on silicon wafers. Other names for overlay registration include, registration error and pattern placement error. A typical microelectronic device or circuit may consist of 20-30 levels or pattern layers. The placement of patterned features on other levels must match the placement of corresponding features on other levels, commonly referred to as overlap, within an accuracy which is some fraction of the minimum feature size or critical dimension (CD).
Overlay error is typically, although not exclusively, measured with an optical overlay metrology tool. See Semiconductor Pattern Overlay, N. Sullivan, SPIE Vol. 3051, 426:432, 1997; Accuracy of Overlay Measurements: Tool and Mark Asymmetry Effects, A. Starikov et al., Optical Engineering, 1298:1309, 1992; KLA 5105 Overlay Brochure, KLA-Tencor; KLA 5200 Overlay Brochure, KLA Tencor; Quaestor Q7 Brochures, Bio-rad Semiconductor Systems. Lithographers have crafted a variety of analysis techniques that attempt to separate out systematic process induced overlay error from random process induced error using a variety of statistical methods. See A Computer Aided Engineering Workstation for Registration Control, E. McFadden, C. Ausschnitt, SPIE Vol. 1087, 255:266, 1989; A “Golden Standard” Wafer Design for Optical Stepper Characterization, K. Kenp, C. King, W. W, C. Stager, SPIE Vol. 1464, 260:266, 1991; Matching Performance for Multiple Wafer Steppers using an Advanced Metrology Procedure, M. Van den Brink et al., SPIE Vol. 921, 180:197, 1988; Characterizing Overlay Registration of Concentric 5× and 1× Stepper Exposure Fields Using Interfield Data, F. Goodwin, J. Pellegrini, SPIE Vol. 3050, 407:417, 1997; Super Sparse Overlay Sampling Plans: An Evaluation of Methods and Algorithms for Optimizing Overlay Quality Control and Metrology Tool Throughput, J. Pellegrini, SPIE Vol. 3677, 72:82, 36220.
The importance of overlay error and its impact to yield can be found elsewhere. See Measuring Fab Overlay Programs, R. Martin, X. Chen, I. Goldberger, SPIE Conference on Metrology, Inspection, and Process Control for Microlithography XIII, 64:71, March 1999; A New Approach to Correlating Overlay and Yield, M. Preil, J. McCormack, SPIE Conference on Metrology, Inspection, and Process Control for Microlithography XIII, 208:216, March 1999. Lithographers have created statistical computer algorithms (for example, Klass II (See Lens Matching and Distortion Testing in a Multi-Stepper, Sub-Micron Environment, A. Yost et al., SPIE Vol. 1087, 233:244, 1989) and Monolith (See A Computer Aided Engineering Workstation for Registration Control, supra)) that attempt to separate out correctable sources of pattern placement error from non-correctable sources of error. See Analysis of overlay distortion patterns, J. Armitage, J. Kirk, SPIE Vol. 921, 207:221, 1988; Method to Budget and Optimize Total Device Overlay, C. Progler et al., SPIE Vol. 3679, 193:207, 1999; and System and Method for Optimizing the Grid and Intrafield Registration of Wafer Patterns, J. Pellegrini, U.S. Pat. No. 5,444,538 issued Aug. 22, 1995. Overall theoretical reviews of overlay modeling can be found in See Semiconductor Pattern Overlay, supra; Machine Models and Registration, T. Zavecz, SPIE Critical Reviews Vol. CR52, 134:159.
Typically, most overlay measurements are made on silicon product wafers after each lithographic process, prior to final etch. Product wafers cannot be etched until the alignment attributes or overlay target patterns are properly aligned to the underlying overlay target patterns. Examples of overlay targets are described in Overlay Alignment Measurement of Wafers, N. Bareket, U.S. Pat. No. 6,079,256 issued Jun. 27, 2000 (at
FIG. 1
b
), Matching Management of Multiple Wafer Steppers Using a Stable standard and a Matching Simulator, M. Van den Brink et al., SPIE Vol. 1087, 218:232, 1989; Automated Electrical Measurements of Registration Errors in Step and Repeat Optical Lithography Systems, T. Hasan et al., IEEE Transactions on Electron Devices, Vol. ED-27, No. 12, 2304:2312, December 1980; Method of Measuring Bias and Edge Overlay Error for Sub 0.5 Micron Ground Rules, C. Ausschnitt et al., U.S. Pat. No. 5,757,507 issued May 26, 1998; Capacitor Circuit Structure for Determining Overlay Error, K. Tzeng et al., U.S. Pat. No. 6,143,621 issued Nov. 7, 2000.
Generally, manufacturing facilities rely heavily on exposure tool alignment, wafer stage matching and calibration procedures (See Stepper Matching for Optimum Line Performance, T. Dooly, Y. Yang, SPIE Vol. 3051, 426:432, 1997; Matching Management of Multiple Wafer Steppers Using a Stable standard and a Matching Simulator, supra), Matching Performance for Multiple Wafer Steppers using and Advanced Metrology Procedure, supra) to help insure that the stepper or scanner tools are aligning properly; inaccurate overlay modeling algorithms can corrupt the exposure tool calibration procedures and degrade the alignment accuracy of the exposure tool system. See Characterizing Overlay Registration of Concentric 5× and 1× Stepper Exposure Fields Using Interfield Data, supra.
Over the past 30 years the microelectronics industry has experienced dramatic, and rapid decreases in critical dimension in part due to improving lithographic imaging systems. See A New Lens for Submicron Lithography and its Consequences for Wafer Stepper Design, J. Biesterbos et al., SPIE Vol. 633, Optical Microlithography V, 34:43, 1986; New 0.54 Aperture I-Line Wafer Stepper with Field by Field Leveling Combined with Global Alignment, M. Van den Brink, B. Katz, S. Wittekoek, SPIE Vol. 1463, 709:724; Step and Scan and Step and Repeat, a Technology Comparison, M. Van den Brink et al., SPIE Vol. 2726, 734:753; 0.7 NA DUV Step and Scan System for 150 nm Imaging with Improved Overlay, J. V. School, SPIE Vol. 3679, 448:463, 1999. Today, these photolithographic exposure tools or machines are pushed to their performance limits. As the critical dimensions of semiconductor devices approach 50 nm the overlay error requirements will soon approach atomic dimensions. See Life Beyond Mix-and-Match: Controlling Sub-0.18 Micron Overlay Errors, T. Zavecz, Semiconductor International, July 2000. To meet the needs of next generation device specifications new overlay methodologies need to be developed. In particular, overlay methodologies that can accurately separate out systematic and random effects and break them into assignable causes may greatly improve device process yields. See A New Approach to Correlating Overlay and Yield, supra; Expanding Capabilities in Existing Fabs with Lithography Tool-Matching, F. Goodwin et al., Solid State Technology, 97:106, June 2000; Super Sparse Overlay Sampling Plans: An Evaluation of Methods and Algorithms for Optimizing Overlay Quality Control and Metrology Tool Throughput, supra; Lens Matching and Distortion Testing in a Multi-Stepper, Sub-Micron Environment, supra.
New “mix and match” technologies that can quickly and accurately reduce the registration error through b

Affiliated with

Also associated with

Rating

Reference wafer and process for manufacturing same does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Reference wafer and process for manufacturing same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reference wafer and process for manufacturing same will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3196992