Method and apparatus for utilizing integrated metrology data...

Data processing: generic control systems or specific application – Specific application – apparatus or process – Product assembly or manufacturing

Reexamination Certificate

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Details

C700S110000, C438S014000

Reexamination Certificate

active

06708075

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor manufacturing, and, more particularly, to a method and apparatus using metrology data from an integrated source for feed-forward data for down-stream processing.
2. Description of the Related Art
The technology explosion in the manufacturing industry has resulted in many new and innovative manufacturing processes. Today's manufacturing processes, particularly semiconductor manufacturing processes, call for a large number of important steps. These process steps are usually vital, and therefore, require a number of inputs that are generally fine-tuned to maintain proper manufacturing control.
The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.
Generally, a set of processing steps is performed on a group of semiconductor wafers, sometimes referred to as a lot. For example, a process layer composed of a variety of materials may be formed above a wafer. Thereafter, a patterned layer of photoresist may be formed above the process layer using known photolithography techniques. Typically, an etch process is then performed on the process layer using the patterned layer of photoresist as a mask. This etching process results in formation of various features or objects in the process layer. Such features may be used for a gate electrode structure for transistors. Many times, trench structures are also formed on the substrate of the semiconductor wafer to isolate electrical areas on a semiconductor wafer. One example of an isolation structure is a shallow trench isolation (STI) structure, which can be used. Typically, STI structures formed on the semiconductor wafers by forming trenches in the wafer and filling such trenches with an insulating material, such as silicon dioxide.
The manufacturing tools within a semiconductor manufacturing facility typically communicate with a manufacturing framework or a network of processing modules. Each manufacturing tool is generally connected to an equipment interface. The equipment interface is connected to a machine interface to which a manufacturing network is connected, thereby facilitating communications between the manufacturing tool and the manufacturing framework. The machine interface can generally be part of an advanced process control (APC) system. The APC system initiates a control script, which can be a software program that automatically retrieves the data needed to execute a manufacturing process.
FIG. 1
illustrates a typical semiconductor wafer
105
. The wafer
105
typically includes a plurality of individual semiconductor die
103
arranged in a grid
150
. Photolithography steps are typically performed by a stepper on approximately one to four die locations at a time, depending on the specific photomask employed. Photolithography steps are generally performed to form a patterned layer of photoresist above one or more process layers that are to be patterned. The patterned photoresist layer can be used as a mask during etching processes, wet or dry, performed on the underlying layer or layers of material, e.g., a layer of polysilicon, metal or insulating material, to transfer the desired pattern to the underlying layer. The patterned layer of photoresist is comprised of a plurality of features, e.g., line-type features, such as a polysilicon line, or opening-type features, that are to be replicated in an underlying process layer.
Turning now to
FIG. 2
, one example of a block diagram representation of a typical manufacturing process flow is illustrated. A manufacturing system
200
prompts a first processing tool
210
to perform a first processes (block
210
). A manufacturing data acquisition tool
220
(e.g., a metrology tool) then analyzes at least some of the processed semiconductor wafers
105
. Wafers
105
upon which the first processing operation are analyzed by the manufacturing data acquisition tool
220
to acquire manufacturing data that can be analyzed (block
240
).
The analyzed data can be then used to adjust various parameters related to manufacturing control of subsequent processes, in order to reduce the effects of existing manufacturing errors. Once the manufacturing data analysis is performed, manufacturing data for feed-forward corrections is made available to the system
200
(block
250
). The system
200
then uses the feed-forward data to perform corrections on subsequent processes performed by a processing tool.
Generally, feed-forward data that is used to correct process deviations to reduce the effects of errors is acquired in an offline manner. For example, once a particular process is performed on a lot of semiconductor wafers
105
, the manufacturing procedure is temporarily interrupted while manufacturing data is acquired. The manufacturing data is then analyzed to produce possible feed-forward correction data to subsequent processing performed on the lot of semiconductor wafers
105
.
The interruption suffered by the manufacturing line to produce feed-forward data can cause inefficiencies in a manufacturing environment. Any pause or interruption in manufacturing can be costly and can cause further deviations in critical accuracies that are needed for proper manufacturing of semiconductor wafers
105
. Furthermore, the feed-forward correction data that is produced by the manufacturing system
200
of
FIG. 2
is generally available too late for use in a second processing operation, or else the second processing operation may be delayed for an undesirable period of time awaiting such data. Thus, semiconductor wafers
105
with non-corrected errors may be produced by the manufacturing system
200
. Devices produced from the processed semiconductor wafers
105
may contain excessive amounts of errors, which can adversely affect the overall yield of the manufacturing process. Furthermore, inefficiencies due to many of the current manufacturing correction procedures can prove to be very costly.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a method is provided for performing feed-forward correction during semiconductor wafer manufacturing. A first process on a semiconductor wafer is performed. Integrated metrology data related to the first process of the semiconductor wafer is acquired. An integrated metrology feed-forward process is performed based upon the integrated metrology data, the integrated metrology feed-forward process comprising identifying at least one error on the semiconductor wafer based upon the integrated metrology data related to the first process of the semiconductor wafer and performing an adjustment process to a second process to be performed on the wafer to compensate for the error. The second process on the semiconductor wafer is performed based upon the adjustment process.
In another aspect of the present invention, a system is provided for performing feed-forward correction during semiconductor wafer manufacturing. The system of the present invention comprises a process controller to perform an integrated metrology feed-forward operation, the integrated metrology feed-forward operation comprising: acquiring integrated metrology data related to a first process of a semiconductor; identifying an error on the semiconductor wafer based upon the integrated metrology data related the first process; calculating a compensation factor for reducing an effect of the identified error; modifying a contr

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