Overvoltage protection circuits that utilize capacitively...

Details Overvoltage protection circuits that utilize capacitively... Overvoltage protection circuits that utilize capacitively...

2001-06-26

2004-09-28

Sircus, Brian (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S111000

Reexamination Certificate

active

06798629

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to integrated circuit devices and, more particularly, to integrated circuits that provide overvoltage protection.
BACKGROUND OF THE INVENTION
Signal buffers are frequently coupled to input or input/output pads on an integrated circuit substrate so that external signals having voltage swings that are incompatible with the voltage levels used by devices on the integrated substrate can be level shifted and/or compressed to compatible levels. Hereinafter, input and input/output pads will be referred to as I/O pads. As illustrated by
FIG. 1
, a conventional CMOS input stage
100
may be used as a buffer for external signals received at an I/O pad
101
. The CMOS input stage
100
may comprise a CMOS inverter
102
having an input connected to the I/O pad
101
. As will be understood by those skilled in the art, the CMOS inverter
102
comprises a PMOS pull-up transistor
103
and an NMOS pull-down transistor
104
. The output
105
of the CMOS inverter
102
is electrically connected to the drain of the NMOS pull-down transistor
104
and to the drain of the PMOS pull-up transistor
103
, as illustrated. Because the PMOS pull-up transistor
103
and NMOS pull-down transistor
104
are connected in a totem pole arrangement between a positive power supply line and a ground reference potential, the voltage swing at the output
105
of the CMOS inverter
102
ranges from a minimum value of 0 Volts to a maximum value equal to the value of the positive power supply line Vdd.
Unfortunately, if an external signal received by the I/O pad
101
has an excessive positive voltage swing, the gate-to-drain voltage V
GD
across the PMOS pull-up transistor
103
and the gate-to-source voltage V
GS
and the gate-to-drain voltage V
GD
across the NMOS pull-down transistor
104
may exceed the ratings of these transistors and cause device breakdown. Moreover, even if the maximum voltage supplied by the external signal to the CMOS inverter
102
is not sufficient to cause breakdown, it may be high enough to cause degradation of the transfer characteristics of the CMOS inverter
102
if exposure to the high external signal is prolonged.
Attempts have been made to protect input buffers from external signals having excessive voltages. One such attempt is disclosed in U.S. Pat. No. 5,319,259 to Merrill, entitled “Low Voltage Input and Output Circuits With Overvoltage Protection”. As illustrated by
FIG. 2
, which is a reproduction of
FIG. 9
from the '259 patent, an input stage
210
includes an input pad
200
, a zener diode
201
, an NMOS pass transistor
202
, a supply terminal
203
, a PMOS feedback transistor
204
and a CMOS inverter
205
. The CMOS inverter
205
comprises an NMOS pull-down transistor
208
connected in a totem pole arrangement with a PMOS pull-up transistor
207
. As illustrated, the PMOS feedback transistor
204
is electrically connected between an input
209
of the CMOS inverter
205
and the positive supply terminal
203
. A gate of the PMOS feedback transistor
204
is electrically connected to an output
206
of the CMOS inverter
205
.
As will be understood by those skilled in the art, the zener diode
201
provides overvoltage protection for external signals having voltages in excess of about six (6) Volts. However, the NMOS pass transistor
202
provides overvoltage protection for external signals having voltages in a range between about six (6) Volts and the magnitude of the power supply voltage Vdd applied to the supply terminal
203
. For example, if an external signal having a voltage of 5 Volts is applied to the input pad
200
and the operating supply voltage is 2.5 Volts, the NMOS pass transistor
202
will initially reduce the 5 Volt signal level to an input node
209
at the input
209
that is equal to Vdd−V
TH-pass
, where V
TH-pass
is the threshold voltage of the NMOS pass transistor
202
, perhaps 0.5 Volts. The voltage V
209
at the input of the CMOS inverter
205
is sufficient to cause the output
206
of the CMOS inverter
205
to be pulled down to a logic 0 level. As illustrated, the logic 0 signal at the output
206
is fed back to the PMOS feedback transistor
204
, which then turns on to pull input node
209
up to the full supply voltage Vdd.
The PMOS feedback transistor
204
should be designed to have relatively weak pull-up characteristics so that an external signal transitioning from a logic 1 level to a logic 0 level will be able to overcome the pull-up logic force provided by the PMOS feedback transistor
204
. The PMOS feedback transistor
204
may be made relatively weak by making its channel relatively long or relatively narrow. Unfortunately, when an external signal transitions from a logic 1 level to a logic 0 level, the NMOS pass transistor
202
and the PMOS feedback transistor
204
initially operate as a pair of resistors connected in series between the input pad
200
and the supply terminal
203
. This series resistive path to Vdd slows the pull-down transition. More significantly, the series resistive path prevents the input from meeting a typical input specification of nominally zero current, which presents a marketing problem for a product using this circuit.
Thus, notwithstanding these attempts to provide signal buffers that are capable of compressing external signal levels to internal voltages that are compatible with on-chip circuitry, there continues to be a need for signal buffers that occupy low area, have low power consumption requirements and limit all gate-to-source, gate-to-drain and drain-to-source voltages to safe voltages for the transistors contained therein.
SUMMARY OF THE INVENTION
Overvoltage protection circuits according to embodiments of the present invention protect devices connected thereto by clamping input signals having excessive positive voltages in an efficient manner that does not damage either the overvoltage protection circuit itself or the other circuits connected thereto. One preferred overvoltage protection circuit includes a first NMOS pass transistor connected between an input signal line (IN) and an output signal line (OUT) to which an input of a load or logic device (e.g., inverter, multi-input logic gate) is connected. A gate of the first pass transistor is preferably connected to a signal line upon which a variable positive voltage level is maintained.
When an input signal (Vin) having a logic 0 level (low voltage) is provided to the input signal line IN, the first pass transistor operates as a normally-on transistor that passes the input signal Vin directly to the output signal line OUT. However, as the input signal Vin transitions from a logic 0 level to a voltage level above a supply voltage Vdd during a pull-up interval, the first pass transistor transitions from a highly conductive on-state to an off-state. In particular, the first pass transistor transitions to an off-state when a positive voltage on the output signal line OUT equals Vgate−Vth, where Vgate is the gate voltage of the first pass transistor and Vth is a threshold voltage of the first pass transistor. At this point, the first pass transistor blocks further increases in the magnitude of the input signal Vin from being passed to the output signal line OUT. By action of the first pass transistor, the output signal line OUT is thereby clamped at a maximum level of Vgate−Vth, with further increases in Vin appearing across the drain and source terminals of the first pass transistor.
To prevent clamping of the output signal line OUT at a positive voltage below Vdd, it is advantageous to provide a gate voltage of the first pass transistor above Vdd, because the source voltage can follow the drain voltage only to the gate voltage less the threshold voltage of the first pass transistor. To achieve this goal, the gate of the first pass transistor is connected to a circuit that clamps the gate of the first pass transistor within a range of voltages. This range of gate voltages extends from a minimum clamped level to a maximum clamped level. In particular, a

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