Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

Filed on

2003-05-06

Date issued

2004-07-13

Examiner

Mai, Son (Department: 2818)

Patent Class

Static information storage and retrieval

SubClass

Addressing

SubSubClass

Particular decoder or driver circuit

Other Related Categories

C365S200000, C365S203000

Type

Reexamination Certificate

Status

active

Patent number

06762971

Description

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device having a redundancy repair circuit.
In general, a semiconductor memory device such as a static random access memory (SRAM) and a dynamic random access memory (DRAM) places an auxiliary memory cell array in addition to a regular memory cell array in order to improve its yield. When it is determined that a defective memory cell exists in the regular memory cell array in the testing process of the semiconductor memory device, the defective memory cell is replaced with the auxiliary memory cell, thereby to complete the semiconductor memory device as a non-defective unit. That is, so-called redundancy repair is performed.
The technology of a prior art semiconductor memory device will be explained below.
FIG. 7
is a configuration view of the prior art semiconductor memory device (SRAM). The semiconductor memory device in
FIG. 7
has memory cells
1
, word-line drivers
2
, a redundant word-line driver
3
, a bit-line precharge control signal line driver
4
, bit-line precharge circuits
5
, word lines WL
1
and WL
2
, a redundant word-line RWL, pairs of bit lines BL
1
, /BL
1
and BL
2
, /BL
2
, and a bit-line precharge control signal line PCGL.
WLCG
1
to WLCG
3
and PCG designate word-line control signals and a bit-line precharge control signal, respectively, and mark A indicates a break in the word line.
The word-line drivers
2
are buffers connected to the respective word lines WL
1
, WL
2
and transmit the respective word-line control signals WLCG
1
, WLCG
2
inputted to each memory cell
1
through the respective word lines WL
1
, WL
2
.
The redundant word-line driver
3
is a buffer connected to the redundant word-line RWL, and in the case where a defect exists in the word line WL
1
or WL
2
, the driver
3
transmits the inputted word-line control signal WLCG
3
to each memory cell
1
through the redundant word-line RWL.
The bit-line precharge control signal line driver
4
is a buffer connected to the bit-line precharge control signal line PCGL, outputs the inputted bit-line precharge control signal PCG to the bit-line precharge control signal line PCGL and activates or deactivates the bit-line precharge circuits
5
.
Each memory cell
1
is connected to a word line (including a redundant word line) and a pair of bit lines.
FIG. 8
is a circuit diagram showing the specific configuration of the memory cell
1
. In
FIG. 8
, Q
1
and Q
2
are access transistors, Q
3
and Q
4
are drive transistors, Q
5
and Q
6
are load transistors, WL is a word line, BL and /BL are a pair of bit lines, and VDD is a power source terminal.
Gate terminals of the access transistors Q
1
and Q
2
are connected to the word line WL or the redundant word line RWL and drain terminals thereof are connected to the pair of bit lines BL and /BL, respectively.
The drive transistor Q
3
and the load transistor Q
5
form a first inverter and the drive transistor Q
4
and the load transistor Q
6
form a second inverter.
An output terminal of the first inverter is connected to an input terminal of the second inverter and an output terminal of the second inverter is connected to an input terminal of the first inverter so that a latch circuit is constituted. The latch circuit stores and holds data. When the word line WL or redundant word line RWL becomes H level, the memory cells
1
connected to the line output data stored therein to the pair of bit lines BL and /BL or receive complementary signals (data) transmitted through the pairs of bit lines BL and /BL.
FIG. 9
is a circuit diagram showing the specific configuration of the bit-line precharge circuit
5
. In
FIG. 9
, Q
7
and Q
8
are precharge transistors, Q
9
is an equalize transistor, BL and /BL are a pair of bit lines, PCGL is a bit-line precharge control signal line, and VDD is a power source terminal.
Each gate terminal of the precharge transistors Q
7
, Q
8
and the equalize transistor Q
9
are connected to the bit-line precharge control signal line PCGL and receives input of the bit-line precharge control signal. Drain terminals of the precharge transistors Q
7
and Q
8
are connected to the pair of bit lines BL and /BL, respectively and source terminals are connected to the power source terminal VDD. The source terminal and drain terminal of the equalize transistor Q
9
are connected to the pair of bit lines BL and /BL, respectively.
When the bit-line precharge control signal PCG is L level, the bit-line precharge circuit
5
becomes activated and precharges pairs of bit lines BL
1
, /BL and BL
2
, /BL
2
. When the bit-line precharge control signal PCG is H level, the bit-line precharge circuit
5
becomes deactivated and goes into a high impedance state.
Operations of the semiconductor memory device thus constituted will be described below. Firstly, the case where no break A occurs in the word line will be explained.
When all of the word-line drivers
2
and the redundant word-line driver
3
output the word-line control signals WLCG
1
to WLCG
3
of L level, all memory cells
1
go into a high impedance state (the state in which data input/output is not performed). At that time, the bit-line precharge control signal PCG (output signal of the bit-line precharge control signal line driver
4
) becomes L level and the bit-line precharge circuit
5
goes into an activated state. All pairs of bit lines BL and /BL are precharged to H level (VDD level) by the bit-line precharge circuits
5
.
Next, when the bit-line precharge control signal PCG becomes H level, the bit-line precharge circuits
5
go into a deactivated state (high-impedance state).
When any one of all of the word-line drivers
2
and the redundant word-line driver
3
outputs H level, the memory cell
1
to which H level is inputted through the word line WL or RWL becomes activated (writing or reading of data is carried out). In the memory cell
1
which receives input of the word-line control signal WLCG of H level, gates of the access transistors Q
1
and Q
2
turns ON and writing or reading data to/from the latch circuit Q
3
to Q
6
is performed through the pair of bit lines BL and /BL connected to the access transistors Q
1
and Q
2
, respectively.
When writing or reading data to/from the memory cell
1
is completed, the word-line control signal WLCG returns to L level from H level and the memory cell
1
goes into a high impedance state. The bit-line precharge control signal PCG becomes L level again and the bit-line precharge circuits
5
are activated, so that the pairs of bit lines BL and /BL are precharged to H level. Subsequently, the above-mentioned processing is repeated.
Next, the case where a break A occurs in the word line will be explained.
Suppose that a break occurs at the point indicated as A in FIG.
7
. Even if the word-line driver
2
transmits the word-line control signal of H level through the word line WL
1
with the break, it is impossible to properly write and read data to/from the memory cell connected to the word line WL
1
on the right side from the break point A.
In such a case, by performing redundancy repair generally according to the below-mentioned method, a non-defective semiconductor memory device is achieved. The word line WL
1
with the break is made to L level (the input terminal of the word line driver
2
connected to the word-line WL
1
is grounded) and all memory cells
1
connected to the word line WL
1
are made to be in a high impedance state. The word-line control signal WLCG which were inputted to the word-line driver
2
of the word line WL
1
if it were not for the break is inputted to the redundant word-line driver
3
. The redundant word-line driver
3
transmits the word-line control signal WLCG to the memory cells
1
through the redundant word line RWL, whereby that writing or reading data is performed in the memory cells
1
connected to the redundant word line RWL. By replacing the memory cells
1
connected to the word line WL
1
having the break with the memory cells
1
connected to the redundant word line RWL, the semiconduct

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