Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2002-08-01
2004-01-06
Fahmy, Wael (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S741000, C257S751000, C257S753000, C257S758000, C257S761000, C257S762000, C257S764000, C438S622000, C438S625000, C438S627000, C438S638000, C438S687000
Reexamination Certificate
active
06674171
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device, and more specifically, it relates to a semiconductor device improved to be capable of implementing an excellent wiring circuit and obtaining a highly integrated semiconductor circuit.
2. Description of the Background Art
Following refinement of a semiconductor device, a wire having low resistance and high reliability must be formed in a wiring step. Copper (Cu) is listed as a material satisfying such requirement for the wire. However, copper diffuses into a conductive impurity region formed on a semiconductor substrate from a copper wire connected to the impurity region, to deteriorate diffused junction. Thus, it is difficult to form an excellent impurity region and an excellent wire including a desired connection hole.
A conventional method of fabricating a semiconductor device is now described with reference to FIG.
6
.
Referring to
FIG. 6
, an impurity region
102
is selectively formed on the surface of a semiconductor substrate
101
. An insulating layer
103
of silicon oxide is formed by CVD (chemical vapor deposition) in a thickness of 500 to 1500 nm, for example, to cover the surface of the semiconductor substrate
101
. Thereafter the insulating layer
103
is patterned by photolithography and etching, for forming a connection hole
104
vertically passing through the insulating layer
103
. Further, a trench
105
for defining a wiring layer is formed in the surface of the insulating layer
103
by photolithography and etching, to cover the upper portion of the connection hole
104
.
Then, the inner wall surface and the bottom surface of the trench
105
as well as the inner wall surface and the bottom surface of the connection hole
104
are covered with a barrier metal film
106
by PVD (physical vapor deposition) or the like. Thereafter a copper wire
107
serving as a conductive film is embedded in the trench
106
and the connection hole
104
.
Then, excess parts of the copper wire
107
and the barrier metal film
106
other than those located on the trench
106
are removed from the upper surface of the insulating layer
103
. Thus, the copper wire
107
is completed.
Another conventional method of fabricating a semiconductor device is described with reference to FIG.
7
.
A semiconductor substrate
101
selectively formed with an impurity region
102
is prepared. An insulating layer
103
of silicon oxide is formed by CVD in a thickness of about 500 to 1500 nm, for example, to cover the surface of the semiconductor substrate
101
. Thereafter the insulating layer
103
is patterned by photolithography and etching for forming a connection hole
104
vertically passing through the insulating layer
103
. Then, a barrier metal film
108
is formed on the inner wall surface and the bottom surface of the connection hole
104
by CVD or PVD, and a tungsten film
109
is thereafter embedded in the connection hole
104
by CVD. Then, excess parts of the tungsten film
109
and the barrier metal film
108
are removed from the upper surface of the insulating layer
103
by dry etching or CMP. Thus, a plug filled up with tungsten is formed.
Then, a silicon oxide film
110
is formed on the insulating layer
103
in a thickness of 500 to 1500 nm, for example. Thereafter the silicon oxide film
110
is patterned by photolithography and etching for forming a trench
111
for defining a wiring layer to expose the connection hole
104
.
Then, a barrier metal film
112
is formed on the overall surface of the semiconductor substrate
101
by PVD, to cover the inner wall surface and the bottom surface of the trench
111
. Thereafter a copper wire
113
serving as a conductive film is embedded in the trench
111
by plating. Then, excess parts of the copper wire
113
and the barrier metal film
112
are removed from the upper surface of the silicon oxide film
110
by dry etching or CMP. Thus, the copper wire
113
is completed.
The conventional semiconductor device is fabricated in the aforementioned manner.
In the semiconductor device shown in
FIG. 6
, however, it is difficult to form the barrier metal film
106
in a thickness sufficient for preventing diffusion of copper from the copper wire
107
. Therefore, copper disadvantageously diffuses into the impurity region
102
from the copper wire
107
to deteriorate diffused junction between the impurity region
102
and the semiconductor substrate
101
.
The semiconductor device shown in
FIG. 7
has been proposed in order to solve this problem. According to this prior art, a tungsten plug can be formed in the connection hole
104
while the barrier metal film
112
having a sufficient thickness can be formed on the bottom of the connection hole
111
, whereby the copper wire
107
can be prevented from diffusion of copper. However, this method requires steps of forming the barrier metal film
108
and forming the tungsten film
109
as well as a CMP removal step for removing the excess parts of the barrier metal film
108
and the tungsten film
109
other than those located on the connection hole
104
from the upper surface of the silicon oxide film
103
. In this method, therefore, the number of process steps is increased beyond the number of steps in the method of fabricating the semiconductor device shown in
FIG. 6
, to disadvantageously reduce productivity.
SUMMARY OF THE INVENTION
The present invention has been proposed in order to solve the aforementioned problems, and an object thereof is to provide a semiconductor device improved to be capable of efficiently preventing diffusion of copper from a copper wire.
Another object of the present invention is to provide a semiconductor device not reduced in productivity.
A semiconductor device according to a first aspect of the present invention comprises a semiconductor substrate. An impurity region is formed on the surface of the aforementioned semiconductor substrate. An insulating layer is provided on the aforementioned semiconductor substrate to cover the aforementioned impurity region. A trench for defining a wiring layer is provided on the surface of the aforementioned insulating layer. A connection hole connecting the aforementioned trench and the aforementioned impurity region with each other is provided in the aforementioned insulating layer. A conductive layer made of a high melting point metal and/or a compound thereof is embedded in the aforementioned connection hole. A wiring layer is formed in the aforementioned trench to be electrically connected to the aforementioned conductive layer.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 6153519 (2000-11-01), Jain et al.
patent: 6451181 (2002-09-01), Denning et al.
patent: 2002/0180044 (2002-12-01), Lu et al.
patent: 7-226387 (1995-08-01), None
Fahmy Wael
McDermott & Will & Emery
Pham Thanhha S
Renesas Technology Corp.
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