BGA type semiconductor device and electronic equipment using...

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead

Reexamination Certificate

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C257S692000

Reexamination Certificate

active

06734545

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to semiconductor devices and electronic equipment or apparatuses using such semiconductor devices and more particularly, to a semiconductor device which operates at a very high speed and realizes a very high integration density and also to electronic equipment or apparatuses using such semiconductor devices.
Electronic equipment have been significantly advanced and remarkable progresses have been continued in recent years particularly in improving an operational speed or in achieving a higher integration. When high-speed electronic equipment is available, various sorts of processings can be realized easily and inexpensively. Further, improvement of the integration density enables realization of a sophisticated function. This tendency is remarkable, in particular, in a semiconductor device field. In this way, the improvement in the operational speed of electronic circuits, electronic equipment and semiconductor devices as well as the higher integration thereof are becoming the motive of advances and developments of the electronic industry.
A higher integration of semiconductor device increases the number of circuits to be incorporated in the device to thereby increase the number of pins of the semiconductor device necessary for connection with other devices. One of solutions to the above problem is disclosed in the specification of U.S. Pat. No. 5,216,278 which is directed to such a technique as to employ a ball grid array (BGA) package. The semiconductor device is accommodated in the BGA package to thereby form a BGA type semiconductor device.
Explanation will be made as to a prior art BGA type semiconductor device with reference to drawings.
FIG. 9
is a top view of a BGA board
1
for use in a BGA type semiconductor device. In the figure, a BGA board
1
is a wiring board which comprises a printed circuit board of organic material or ceramic. It is the semiconductor element that is mounted at a semiconductor device mounting area or position
5
in the center of the BGA board
1
. Bonding pads
4
are provided on the BGA board
1
for bonding. The pads
4
and electrodes on the semiconductor element are electrically connected by bonding wires or the like. Extended substantially radially from the respective bonding pads
4
are a pattern of wires
3
which in turn are connected at their one ends with associated through holes
2
. The density of the patterned wires
3
is high in the center of the BGA board
1
. For the purpose of avoiding this, the through holes
2
are arranged along the outer periphery of the BGA board
1
.
FIG. 10
shows a rear view of the BGA board
1
. In the figure, the through holes
2
are used to interconnect the front and rear wiring lines of the BGA board
1
. More in detail, on the rear side of the BGA board
1
, wiring lines
6
, which extend from the associated through holes
2
, are connected to soldering pads
7
. The pads
7
are arranged in a two-dimensional positional relation. More specifically, in the example of
FIG. 10
, the soldering pads in
3
rows are arranged along the four sides of the board
1
not in a single row but in a two-dimensional arrangement having a width.
FIG. 11
shows a cross-sectional view of a major part of the BGA board
1
under such a condition that a semiconductor element
8
is mounted on the BGA board
1
. Electrodes on the semiconductor element
8
and the bonding pads
4
on the bonding pads
4
are connected by bonding wires
9
. The wiring extends from the bonding pads
4
via the patterned wires
3
, through holes
2
and Wiring lines
6
to the soldering pads
7
. Connected to the soldering pads
7
are solder balls
10
. Though not illustrated, the BGA type semiconductor device is mounted on a printed circuit board by means of the solder balls
10
to be electrically connected to other device.
The aforementioned BGA type semiconductor device features that this type of device can have a more increased number of pins than another package such as dual in-line package (DIP) or quad flat package (QFP), under the same outer dimensions. This feature results from the fact that the soldering pads
7
shown in
FIG. 10
are arranged in the 2-dimensional form which does not exist in the other packages. For this reason, even when a higher integration of semiconductor device increases the number of circuits to be incorporated therein and also the number of pins therefor, there can be realized a semiconductor device which prevents its outer dimensions from being made large in scale, which contributes to the advances and developments of the electronic industry.
SUMMARY OF THE INVENTION
However, when a semiconductor device is further improved in its operational speed or when its integration is further enhanced, it may sometimes occur that the conventional BGA type semiconductor device cannot cope with it.
One of important factors upon using the semiconductor device is power supply noise. When the semiconductor device operates, it consumes power. Since current consumption varies depending on the operation of its internal circuits, power supply noise is caused by the impedance of wires in a power supply system. Assuming that power supply noise is denoted by &Dgr;V, the impedance of a power supply system is by Z, and current consumption variation is by &Dgr;I; then a relationship among these 3 factors is expressed by an equation &Dgr;V=Z×&Dgr;I.
In the case of the semiconductor device, the impedance of the power supply system is based on an inductance L of wires within the semiconductor device. Accordingly, assuming that the semiconductor device has an operational frequency f, then the impedance Z of the power supply system satisfies an equation Z=2&pgr;fL.
In the case of the printed circuit board having the semiconductor device mounted thereon, since the impedance of the power supply system is suppressed to a low value by a bypass capacitor, planar power supply/grounding wirings or other means; the impedance of the entire power supply system is, in many cases, based primarily on the inductance L of wires within the semiconductor device.
Therefore, as expressed by &Dgr;V=2&pgr;fL×&Dgr;I, the power supply noise &Dgr;V is generated by the operational frequency f, the inductance L of wires within the semiconductor device and the current consumption variation component &Dgr;I.
When the power supply noise becomes excessive, the semiconductor device erroneously operates. This is because a power supply voltage deviates from a normal operational range of the circuit within the semiconductor device, or the power supply noise is superimposed on signal wirings to cause erroneous operation of other circuits. For this reason, if the power noise is not suppressed to a prescribed value or less, erroneous operation occurs in the semiconductor device, thus disabling use of the device.
When the operational frequency f of the semiconductor device is increased, this causes an increase of the power supply noise in accordance with the aforementioned equation &Dgr;V=2&pgr;fL×&Dgr;I and thus the erroneous operation of the semiconductor device, which sometimes results in that the semiconductor device becomes impossible to use.
Further, when a higher integration of semiconductor device and an increase in the number of circuits to be incorporated therein result in an increase in the current consumption, this also causes an increase of the current consumption variation &Dgr;I. Thus, the power supply noise increases in accordance with the above equation &Dgr;V=2&pgr;fL×&Dgr;I and erroneous operation takes place in the semiconductor device, thus leading to disabled use of the semiconductor device.
Furthermore, in the case of, in particular, a CMOS semiconductor device, improvement in the operational frequency f of the semiconductor device causes the current consumption to increase in proportion to the frequency. This also results in that the power consumption variation &Dgr;I is increased to increase the power supply noise in accordanc

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