Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
2002-07-24
2004-07-20
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C438S017000, C438S014000, C257S777000, C257S784000
Reexamination Certificate
active
06764879
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a COC (Chip On Chip) type semiconductor device in which two semiconductor chips, each including a semiconductor integrated circuit formed on the upper surface thereof, are attached together by flip chip bonding.
In recent years, various efforts have been made in the art to realize a lower cost, a smaller size and a higher performance (e.g., a higher speed, and a lower power consumption) for a semiconductor device including an integrated circuit. For example, a COC type semiconductor device has been proposed in the art, in which two semiconductor chips are attached together by flip chip bonding, the two semiconductor chips including LSIs of different functions or LSIs that are produced by different processes.
A conventional semiconductor device in which two semiconductor chips are attached together by flip chip bonding, and a method for manufacturing the same, will now be described.
FIG. 11A
is a schematic diagram illustrating a semiconductor wafer having formed therein a plurality of semiconductor chip areas each of which is to be a semiconductor chip mounted on a conventional semiconductor device.
FIG. 11B
is a plan view illustrating the upper surface of the semiconductor wafer of
FIG. 11A
on an enlarged scale.
As illustrated in FIG.
11
A and
FIG. 11B
, a plurality of semiconductor chip areas
2
are formed on a semiconductor wafer
1
. The semiconductor chip areas
2
are partitioned from one another by a separation line
3
, and a plurality of electrode pads
4
are formed in each of the semiconductor chip areas
2
. The semiconductor chip areas
2
are cut off from one another along the separation line
3
into semiconductor chips that are each mounted on a conventional semiconductor device.
Each electrode pad
4
formed in a semiconductor chip area
2
is used as an external electrode pad for electrical connection to an external circuit in some cases, and as a probe pad for an electrical inspection of the semiconductor chip in other cases. Thus, each electrode pad functions both as an external electrode pad and as an inspection electrode pad. Note that only the electrode pads
4
are drawn in the semiconductor chip areas
2
in
FIG. 11B
, and other wires, etc., are not shown in the figure.
FIG. 12A
is a schematic diagram illustrating a semiconductor chip
2
a
that has been cut out from the semiconductor wafer
1
and another semiconductor chip
5
, which are to be provided in a conventional semiconductor device, and
FIG. 12B
is a cross-sectional view illustrating the conventional semiconductor device.
As illustrated in FIG.
12
A and
FIG. 12B
, a bump electrode
6
formed on an electrode pad
8
and an external electrode pad
7
are formed on the upper surface of the semiconductor chip
5
. Moreover, a bump electrode
9
is formed on an electrode pad
4
on the upper surface of the semiconductor chip
2
a
. In a conventional semiconductor device
200
, the semiconductor chip
5
and the semiconductor chip
2
a
are attached together by flip chip bonding, with the bump electrode
6
and the bump electrode
9
being connected together. As illustrated in
FIG. 12A
, the semiconductor chip
2
a
is mounted on an area of the upper surface of the semiconductor chip
5
that is indicated by a broken line.
In the conventional semiconductor device
200
, the space between the semiconductor chip
5
and the semiconductor chip
2
a
is filled with an insulative resin
10
, as illustrated in FIG.
12
B. Moreover, the semiconductor chip
5
is fixed on a die pad
11
of a lead frame. Furthermore, the external electrode pad
7
of the semiconductor chip
5
and an inner lead
12
of the lead frame are electrically connected to each other by a thin metal wire
13
. The semiconductor chip
5
, the semiconductor chip
2
a
, the die pad
11
, the inner lead
12
and the thin metal wire
13
are encapsulated by an encapsulation resin
14
.
Next, a method for manufacturing the conventional semiconductor device
200
will be described.
First, an insulative resin is applied on a central portion of the upper surface of the semiconductor chip
5
. Then, the semiconductor chip
2
a
is pressed against the semiconductor chip
5
, and the bump electrode
6
of the semiconductor chip
5
is connected to the bump electrode
9
of the semiconductor chip
2
a
. Note that the insulative resin may alternatively be injected into the space between the semiconductor chip
5
and the semiconductor chip
2
a
after they are connected together by flip chip bonding.
Then, after the external electrode pad
7
of the semiconductor chip
5
and the inner lead
12
of the lead frame are connected to each other by the thin metal wire
13
, the semiconductor chip
2
a
, the semiconductor chip
5
, the die pad
11
, the inner lead
12
and the thin metal wire
13
are encapsulated by the encapsulation resin
14
. Then, an outer lead of the lead frame protruding from the encapsulation resin
14
is shaped, thereby obtaining the semiconductor device
200
.
However, with the conventional semiconductor device
200
, the external electrode pad
7
to which the thin metal wire
13
is connected needs to be provided along the periphery of the semiconductor chip
5
. In addition, the position at which the external electrode pad
7
is provided needs to be outside an area S on which the semiconductor chip
2
a
is to be mounted, as illustrated in FIG.
12
A. Thus, the size of the semiconductor chip
5
needs to be larger than the size of the semiconductor chip
2
a.
A possible way to reduce the size of the semiconductor device is to reduce the size of the semiconductor chip
2
a
and thus the size of the semiconductor chip
5
. However, it is difficult to reduce the size of the semiconductor chip
2
a
for the following reason.
The semiconductor chip areas
2
formed on the semiconductor wafer
1
are electrically inspected by a probing process, and only non-defective semiconductor chip areas are picked up. Then, those semiconductor chip areas
2
that have been picked up are separated, thereby obtaining semiconductor chips
2
a
, each of which is attached to the semiconductor chip
5
by flip chip bonding.
A probe pad is required in order to perform an electrical inspection by a probing process, and some of the electrode pads
4
in each semiconductor chip area
2
(semiconductor chip
2
a
) are probe pads. A probe may slide after contacting the electrode pad
4
being a probe pad. Therefore, in order to ensure that the probe contacts the electrode pad
4
being a probe pad, the electrode pad
4
being a probe pad needs to be formed with a size larger than a square of 70 &mgr;m×70 &mgr;m. This necessarily increases the size of the semiconductor chip
2
a
. Thus, it is difficult to reduce the size of the semiconductor chip
2
a.
Moreover, as semiconductor devices are provided with a higher performance (e.g., a higher speed, and a lower power consumption), the formation of a probe pad in the semiconductor chip area
2
(semiconductor chip
2
a
) makes non-negligible the influence of the capacitance, the inductance, etc., of each of the probe pad, the electrode pad, the protection circuit for the electrode pad, the bump electrode and the wire.
SUMMARY OF THE INVENTION
The present invention has been made to solve the problem in the prior art, and has an object to provide a semiconductor device having a small size and a high performance.
A semiconductor wafer of the present invention includes: a plurality of semiconductor chip areas each of which is to be a semiconductor chip; and a cut-off area for separating the plurality of semiconductor chip areas from one another so as to obtain the semiconductor chips, wherein: an integrated circuit and an electrode pad connected to the integrated circuit are provided in each of the semiconductor chip areas; and a probe pad connected to the electrode pad is provided in the cut-off area.
With the semiconductor wafer of the present invention, the semiconductor wafer is inspected by contacting a probe to the prob
Fujimoto Hiroaki
Nagao Koichi
Everhart Caridad
Matsushita Electric - Industrial Co., Ltd.
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