Flip-chip package substrate

Details Flip-chip package substrate Flip-chip package substrate

2002-06-06

2004-05-25

Cuneo, Kamand (Department: 2827)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S778000

Reexamination Certificate

active

06740965

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the priority benefit of Taiwan application serial no. 91206012, filed Apr. 30, 2002.
BACKGROUND OF INVENTION
1. Field of Invention
The present invention relates to a flip-chip package substrate. More particularly, the present invention relates to a flip-chip package substrate having a lower plane inductance and synchronous switching noise (SSN).
2. Description of Related Art
Flip-chip (FC) bonding is a common type of packaging technique in a chip scale package (CSP). To form a flip-chip package, an array of die pads is formed on the active surface of a die. A bump is formed over each die pad. Finally, the die is flipped over so that the bumps can be attached to corresponding contacts, also known as bump pads, on a carrier. Since a flip-chip package occupies a small area and reduces signal transmission paths, flip-chip bonding technique has been widely adopted to produce various types of chip packages.
FIG. 1
is a schematic cross-sectional view of a conventional flip-chip package. As shown in
FIG. 1
, the flip-chip package includes a flip-chip package substrate
20
and a die
10
. The flip-chip package substrate
20
consists of alternately stacked wiring layers
26
and insulation layers
28
. A plurality of conductive plugs
30
that passes through the insulation layer
28
is used for connecting the wiring layers
26
electrically. In addition, the uppermost surface
22
of the flip-chip package substrate
20
has a plurality of bump pads
34
for connecting with bumps
16
on the die
10
. The bump pads
34
are attached to the uppermost wiring layer
26
(the wiring layer closest to the upper surface
22
). On the other hand, the bumps
16
are attached to the upper surface of the die pads
14
on the active surface
12
of the die
10
. Furthermore, the bump pads
34
on the upper surface
22
of the flip-chip package substrate
20
are wired to the ball pads
36
on the bottom surface
24
through multiples of wiring layers
26
and conductive plugs
30
. The ball pads
36
are attached to the lowest wiring layer (closest to the bottom surface
24
). A conductive structure such as a solder ball may also be attached to each ball pad
36
so that the package is electrically connected to the next level of electronic device. Hence, the die
10
is able to transmit signals to external electronic devices through the flip-chip package substrate
20
.
FIG. 2A
is a top view of the die in FIG.
1
. The active surface
102
of the die
100
in
FIG. 2A
has a plurality of die pads
106
(the die pads
14
in FIG.
1
). According to signaling function (including signal, power, ground and core power/ground) in the die
100
, die pads
106
may be classified into signal pads
106
a
, power pads
106
b
, ground pads
106
c
and core pads
108
. In general, the signal pads
106
a
, the power pads
106
b
and the ground pads
106
c
are distributed outside and around the cored pad region
110
while the core pads
108
are positioned within the core pad region
110
. To collect die pads having identical function in one place, the signal pads
106
a
are enclosed within one or more signal pad rings
112
a
. Similarly, the power pads
106
b
are enclosed within one or more power pad rings
112
b
and the ground pads
106
c
are enclosed within one or more ground pad rings
112
c
. The signal pad rings, the power pad rings
112
b
and the ground pad rings
112
c
are all concentrically laid around the core region
110
on the active surface
102
of the die
100
. Meanwhile, all the core pads
108
are positioned inside the central core region
110
.
FIG. 3A
is a top view of the central portion of the die in
FIG. 1
showing a distribution of core power pads and core ground pads. As shown in
FIG. 3A
, the core pads
108
are divided into core power pads
108
a
and core ground pads
108
b
. The core power pads
108
a
and the core ground pads
108
b
form an alternately positioned array.
FIG. 3B
is a top view of the central portion of the die in
FIG. 1
showing an alternative distribution of core power pads and core ground pads. In
FIG. 3B
, the core power pads
108
a
are grouped together to form at least a core power pad ring
114
a
and core ground pads
108
b
are similarly grouped together to form at least a core ground pad ring
114
b
. Both the core power pad ring
114
a
and the core ground pad ring
114
b
are concentric to the central region of the die.
FIG. 2B
is a top view of a flip-chip package substrate within the package shown in FIG.
1
. The ball pads
136
of a conventional flip-chip package substrate
130
correspond to the signal pads
106
a
, the power pads
106
b
, the ground pads
106
c
and the core power/ground pads
108
in FIG.
2
A. In other words, the ball pads
136
may be classified into signal ball pads
136
a
, power ball pads
136
b
, ground ball pads
136
c
and core ball pads
138
. The core ball pads
138
lies within the core region
140
. However, the signal ball pads
136
a
, the power ball pads
136
b
and the ground ball pads
136
c
are randomly distributed on the bottom surface
134
of the flip-chip package substrate
130
. Hence, there is a mismatch between the ball pads on the substrate
130
and the signal pads
106
a
, the power pads
106
b
and the ground pads
106
c
on the die
100
shown in FIG.
2
A. Ultimately, overall length of wires linking the die pads
106
to the ball pads
136
is increased leading to a longer current path and a greater plane inductance.
SUMMARY OF INVENTION
Accordingly, one object of the present invention is to provide a flip-chip package substrate having ball pads arranged to match the die pads on a die having a multiple pad ring”s structure. Ultimately, overall wiring length from the die pads on the die to the ball pads on the substrate, plane inductance and synchronous switching noise of the package are all reduced while electrical performance of the package is improved.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a flip-chip package substrate. The flip-chip package substrate is a stack structure comprising a plurality of wiring layers such that neighboring wiring layers are separated from each other by an insulation layer. The substrate also includes one or more conductive plugs that pass through the insulation layer for electrically connecting wiring layers. The uppermost wiring layer has a plurality of core bump pads, a plurality of signal bump pads, a plurality of power bump pads and a plurality of ground bump pads. The signal bump pads, the power bump pads and the ground bump pads are grouped together to form one or more signal bump pad rings, one or more power bump pad rings and one or more ground bump pad rings. The signal bump pad rings, the power bump pad rings and the ground bump pad rings are distributed concentrically around the central region of the substrate. In addition, the bottommost wiring layer has a plurality of core ball pads, a plurality of signal ball pads, a plurality of power ball pads and a plurality of ground ball pads. The signal ball pads, the power ball pads and the ground ball pads are grouped together to form one or more signal ball pad rings, one or more power ball pad rings and one or more ground ball pad rings. The signal ball pad rings, the power ball pad rings and the ground ball pad rings are concentrically distributed around the central region of the substrate.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 6225702 (2001-05-01), Nakamura
patent: 6384476 (2002-05-01), Takeuchi
patent: 6388207 (2002-05-01), Figueroa et al.
patent: 6479758 (2002-11-01), Arima et al.

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