Registers – Records – Conductive
Reexamination Certificate
2001-10-17
2004-07-27
Frech, Karl D. (Department: 2876)
Registers
Records
Conductive
C257S351000, C257S357000, C257S296000, C257S298000, C365S052000, C365S185290
Reexamination Certificate
active
06766960
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to integrated circuit smart cards or memory cards, and more particularly, to a smart card storing information in nonvolatile programmable semiconductor memory that uses a breakdown phenomena in an ultra-thin dielectric such as a MOS gate dielectric to store digital information.
BACKGROUND OF THE INVENTION
Integrated circuit smart cards (also known as IC memory cards) are cards about the same size as a credit card and containing at least one integrated circuit having memory. Some smart cards have length and width dimensions corresponding to those of credit cards. The size of such smart cards is determined by an international standard (ISO 7816), which among other specifications, also defines the position of electrical contacts and their functions, and a protocol for communications between the integrated circuit and readers (vending machines, payphones, etc.). The term “smart card”, as used herein, is meant to include cards that include memory, and may or may not include microprocessors, but that do not necessarily conform to ISO 7816. At least part of the memory is programmable to form a read-only memory (ROM), so as to be able to personalize the card. The type of memory used is typically a flash memory or electrically erasable programmable ROM (EEPROM).
The smart cards are gaining acceptance for various applications, including electronic payment systems. Advanced cards are capable of containing electronic “purses”, in addition to other functionalities. Such advanced payment means contain, in addition to memory, a processor capable of running suitable programs. It should be noted that in this text, the terms smart card or card is used to describe a device having at least one integrated electronic circuit comprising at least memory, and typically a processor.
The smart cards that use flash or EEPROM memory are costly because of the special manufacturing processes required to make flash or EEPROM memory. Moreover, flash or EEPROM memory can be erased (or reprogrammed) without indication that a reprogramming has been done. Further, because flash and EEPROM memory is based upon the storage of charge on a floating gate, the stability of the memory over long periods of time or when stressed (either mechanically or by electrical fields) is questionable due to leakage of the charge, through various mechanisms such as stress induced leakage current (SILC).
Other types of smart cards use anti-fuse technology for the smart card memory. For example, U.S. Pat. No. 5,917,229 describes such technology. However, the fabrication of anti-fuse technology is also comparatively expensive and requires special semiconductor manufacturing processes.
Still another type of smart card uses optical based technology, wherein a laser is used to write information onto the smart card. However, the laser smart card is undesirable because the reader/writer for the smart card is comparatively expensive, on the order of thousands of dollars.
The present invention describes a smart card that utilizes a non-volatile memory that can be easily written and read, as well as providing data stability, while still being comparatively inexpensive to manufacture.
As background, non-volatile memory retains stored data when power is removed, which is required or at least highly desirable in many different types of computers and other electronic devices. One commonly available type of nonvolatile memory is the programmable read-only memory (“PROM”), which uses word line—bit line crosspoint elements such as fuses, anti-fuses, and trapped charge devices such as the floating gate avalanche injection metal oxide semiconductor (“FAMOS”) transistor to store logical information. PROM typically is not reprogrammable.
An example of one type of PROM cell that uses the breakdown of a silicon dioxide layer in a capacitor to store digital data is disclosed in U.S. Pat. No. 6,215,140, issued Apr. 10, 2001 to Reisinger et al. The basic PROM disclosed by Reisinger et al. uses a series combination of an oxide capacitor and a junction diode as the crosspoint element. An intact capacitor represents the logic value 0, and an electrically broken-down capacitor represents the logic value 1. The thickness of the silicon dioxide layer is adjusted to obtain the desired operation specifications. Silicon dioxide has a breakdown charge of about 10 C/cm
2
(Coulomb/cm
2
). If a voltage of 10 volts is applied to a capacitor dielectric with a thickness of 10 nm (resultant field strength 10 mV/cm), a current of about 1 mA/cm
2
flows. With 10 volts, this thus results in a substantial amount of time for programming a memory cell. However, it is more advantageous to design the capacitor dielectric to be thinner, in order to reduce the high power loss which occurs during electrical breakdown. For example, a memory cell configuration having a capacitor dielectric with a thickness of 3 to 4 nm can be operated at about 1.5 V. The capacitor dielectric does not yet break down at this voltage, so that 1.5 V is sufficient to read data from the memory cell. Data are stored, for example, at 5 V, in which case one cell strand in a memory cell configuration can be programmed within about 1 ms. The energy loss which occurs in this case per cm
2
of capacitor dielectric is then about 50 Watts (10 Coulomb*5 V). If the desired power loss is about 0.5 W, about 100 s are required to program a 1 Gigabit memory. If the permissible power losses are higher, the programming can be carried out correspondingly more quickly.
Some types of nonvolatile memory are capable of being repeatedly programmed and erased, including erasable programmable read only semiconductor memory generally known as EPROM, and electrically erasable programmable read only semiconductor memory generally known as EEPROM. EPROM memory is erased by application of ultraviolet light and programmed by application of various voltages, while EEPROM memory is both erased and programmed by application of various voltages. EPROMs and EEPROMs have suitable structures, generally known as floating gates, that are charged or discharged in accordance with data to be stored thereon. The charge on the floating gate establishes the threshold voltage, or V
T
, of the device, which is sensed when the memory is read to determine the data stored therein. Typically, efforts are made to minimize gate oxide stress in these types of memory cells.
A device known as a metal nitride oxide silicon (“MNOS”) device has a channel located in silicon between a source and drain and overlain by a gate structure that includes a silicon dioxide layer, a silicon nitride layer, and an aluminum layer. The MNOS device is switchable between two threshold voltage states V
TH(high)
and V
TH(low)
by applying suitable voltage pulses to the gate, which causes electrons to be trapped in the oxide-nitride gate (V
TH(high)
) or driven out of the oxide-nitride gate (V
TH(low)
). Typically, efforts are made to minimize gate oxide stress in these types of memory cells.
A junction breakdown memory cell that uses a stored charge on the gate of a gate controlled diode to store logic 0 and 1 values is disclosed in U.S. Pat. No. 4,037,243, issued Jul. 19, 1977 to Hoffman et al. Charge is stored on the gate by using a capacitance formed between the p-type electrode of the gate controlled diode and the gate electrode. Charge storage is enhanced by using a composite dielectric in the capacitor formed from silicon dioxide and silicon nitride layers in place of silicon dioxide. The application of an erase voltage to the electrode of the gate controlled diode causes the oxide-nitride interface surface to fill with negative charge, which is retained after the erase operation is completed. This negative interface charge causes the gate-controlled diode to operate in an induced junction mode even after the erase voltage is removed. When the gate-controlled diode is thereafter read, it exhibits field-induced junction breakdown of its channel and saturation current flows. The field induced junction breakdown voltage i
Frech Karl D.
Kilopass Technologies, Inc.
Nguyen Kim
Perkins Coie LLP
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