Abrasive tool making process – material – or composition – With inorganic material – Clay – silica – or silicate
Reexamination Certificate
2002-01-16
2004-01-20
Marcheschi, Michael (Department: 1755)
Abrasive tool making process, material, or composition
With inorganic material
Clay, silica, or silicate
C051S307000, C051S309000, C106S003000, C438S692000, C438S693000
Reexamination Certificate
active
06679929
ABSTRACT:
The present invention relates to a polishing composition to be used for polishing substrates for semiconductors, photomasks and various memory hard disks, particularly to a polishing composition useful for polishing for planarization of the surface of device wafers in e.g. semiconductor industry, and a polishing method employing such a composition.
More particularly, the present invention relates to a polishing composition which is highly efficient, provides high selectivity and is applicable to formation of excellent polished surface in the polishing of semiconductor devices to which so-called chemical mechanical polishing (hereinafter referred to as “CMP”) technology is applied, in the processing of device wafers, and a polishing method employing such a composition.
Progress of so-called high technology products including computers has been remarkable in recent years, and parts to be used for such products, such as ULSI devices, have been developed for high integration and high speed, year after year. Along with such progress, the design rule for semiconductor devices has been progressively refined year after year, the depth of focus in a process for producing devices tends to be shallow, and planarization required for the pattern-forming surface tends to be increasingly severe.
Further, to cope with an increase in resistance of the wiring due to refinement of the wiring on the device, it has been studied to employ copper instead of tungsten or aluminum, as the wiring material. By its nature, copper is hardly processable by etching, and accordingly, it requires the following process.
Namely, after forming wiring grooves and vias on an insulating layer, copper wirings are formed by sputtering or plating (so-called damascene method), and then an unnecessary copper layer deposited on the insulating layer is removed by CMP process which is a combination of mechanical polishing and chemical polishing.
However, in such a process, it may happen that copper atoms will diffuse into the insulating layer to deteriorate the device properties. Therefore, for the purpose of preventing diffusion of copper atoms, it has been studied to provide a barrier layer on the insulating layer having wiring grooves or vias formed. As a material for such a barrier layer, metal tantalum or a tantalum compound such as tantalum nitride (hereinafter will generally be referred to as a tantalum-containing compound) is most suitable from the viewpoint of the reliability of the device and is expected to be employed mostly in the future.
Accordingly, in such a CMP process for a semiconductor device containing such a copper layer and a tantalum-containing compound, firstly the copper layer as the outermost layer and then the tantalum-containing compound layer as the barrier layer, are polished, respectively, and polishing will be completed when it has reached the insulating layer of e.g. silicon dioxide or monofluoro silicon oxide. As an ideal process, it is desired that by using only one type of a polishing composition, the copper layer and the tantalum-containing compound layer are uniformly removed by polishing in a single polishing step, and polishing will be completed certainly when it has reached the insulating layer.
However, copper and a tantalum-containing compound are different in their hardness, chemical stability and other mechanical properties and accordingly in the processability, and thus, it is difficult to adopt such an ideal polishing process. Accordingly, the following two step polishing process, i.e. polishing process divided into two steps, is being studied.
Firstly, in the first step polishing (hereinafter referred to as the first polishing), using a polishing composition capable of polishing a copper layer at a high efficiency, the copper layer is polished using e.g. a tantalum-containing compound layer as a stopper until such a tantalum-containing compound layer is reached. Here, for the purpose of not forming various surface damages such as recesses, erosion, dishing, etc., on the copper layer surface, the first polishing may be terminated immediately before reaching the tantalum-containing compound layer i.e. while a copper layer still slightly remains. Then, in the second step polishing (hereinafter referred to as the second polishing), using a polishing composition capable of polishing mainly a tantalum-containing compound layer at a high efficiency, the remaining thin copper layer and the tantalum-containing compound layer are polished using the insulating layer as a stopper, and polishing is completed when it has reached the insulating layer.
Here, dishing, recesses and erosion are surface damages due to excessive polishing of the wiring portion, caused by difference in hardness between a wiring layer (copper in this case) and the insulating layer or the tantalum-containing compound layer, by etching effect to the wiring layer, and mainly by a difference in pressure applied per unit area, respectively, and they decrease the cross-sectional area of the wiring layer. Accordingly, when a device is prepared, they tend to increase the resistance of the wiring at the corresponding portion, or they may cause contact failure in extreme cases. Accordingly, the polishing composition to be used in the first polishing is required to have a property such that it is capable of polishing the copper layer at a high stock removal rate without forming the above-mentioned various surface damages on the copper layer surface, which can not be removed by the second polishing.
With respect to such a polishing composition for a copper layer, for example, JP-A-7-233485 discloses a polishing liquid for a copper type metal layer, which comprises at least one organic acid selected from the group consisting of aminoacetic acid (hereinafter referred to as glycine) and amidesulfuric acid, an oxidizing agent and water, and a method for producing a semiconductor device using such a polishing liquid. Further, JP-A-8-83780 discloses an abrasive which contains aminoacetic acid and/or amidesulfuric acid, an oxidizing agent, water and benzotriazole or its derivative, and a method for producing a semiconductor device using such an abrasive.
However, as a result of the experiments conducted by the present inventors, it has been confirmed that when a copper layer having a pattern formed thereon is polished by using a polishing composition comprising only an abrasive, glycine and hydrogen peroxide, chemical etching effect on copper and erosion on the copper surface after the polishing tend to be significant, and deep recesses are likely to be formed. Further, in a case where benzotriazole having a function to suppress chemical etching effect on copper is incorporated in order to suppress erosion on the copper surface, if the addition amount of benzotriazole is too large, the stock removal rate of the copper layer tends to be significantly low, and the polishing takes long, such being inefficient.
Further, in a case where the addition amount of benzotriazole is too small, no adequate function to suppress chemical etching effect can be obtained, and it is thereby impossible to adequately suppress erosion on the copper surface. The present inventors have conducted experiments and reached such a conclusion that in a case of polishing a copper wiring by using a polishing composition comprising abrasive grains, glycine, benzotriazole and water, no composition can be found out for optimum polishing.
Namely, it has been strongly desired to develop a composition for polishing which has both properties of high stock removal rate of the copper layer and low chemical etching effect on the copper layer.
The present invention has been made to solve the above-described problems. Namely, it is an object of the present invention to provide a polishing composition, with which polishing can be carried out with a high stock removal rate of the copper layer while suppressing a chemical etching effect on the copper layer, in polishing of a wafer having a device pattern containing at least a layer of copper and a layer of a tantalum-containing c
Asano Hiroshi
Ina Katsuyoshi
Sakai Kenji
Fujimi Incorporated
Marcheschi Michael
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