Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-06-21
2004-03-23
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185180, C365S185290
Reexamination Certificate
active
06711058
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an erase method for nonvolatile semiconductor storage devices capable of preventing disturb at erasing, particularly, in floating gate type nonvolatile semiconductor storage devices, and also relates to a row decoder circuit for fulfilling the method.
In recent years, with the trend toward higher integration of flash memories, there has been a demand for lower power consumption. For this purpose, a variety of attempts to achieve lower power consumption have been made by using the FN (Fowler-Nordheim) tunneling phenomenon for program and erase operations. Flash memories using the FN tunneling phenomenon for program and erase operations like this are called FN-FN type flash memories.
Meanwhile, the flash memories can be classified also depending on differences in the structure of memory cell array or the like. The major four classes, as have been announced from various companies, are listed below:
[1] AND type flash memories reported in Technical Report of IEICE (the Institute of Electronics, Information and Communication Engineers of Japan), ICD93-128, p. 37, 1993, “AND Type Cell for 3V Single Power Supply 64 Mbit Flash Memories”;
[2] DINOR type flash memories reported in Technical Report of IEICE, ICD93-26, p. 15, 1993, “3V Single Power Supply DINOR Type Flash Memories”;
[3] DuSNOR type flash memories reported in Technical Digest, pp. 263-266, 1995, “A Novel Dual String NOR (DuSNOR) Memory Cell Technology Scalable to the 256 Mbit and 1 Gbit Flash Memories”; and
[4] ACT (Asymmetrical Contactless Transistor) type flash memories reported in IEDM Technical Digest, pp. 269-270, 1995, “A New Cell Structure for Sub-quarter Micron High Density Flash Memory” or
in Technical Report of ICICE, ICD97-21, p. 37, 1997, “Discussion on Sense Systems for ACT Type Flash Memories”.
In these flash memories, which are electrically programmable and erasable on memory cells, a voltage is applied to the drains/sources or gates of select cells while a voltage is applied also to the drains/sources or gates of non-select memory cells, for program and erase operations. During these operations, there is a possibility that mis-reads occur because threshold of the non-select memory cells would be changed by an effect of the voltage application.
In recent years, a system in which a negative voltage is applied to the substrate (well), has begun to be used in order to reduce the absolute values of voltages used inside the flash memory during the erasing. When a voltage is applied to the substrate (well) in program and erase operations, this applied voltage would cause non-select memory cells to be put into a light erased state as described above, adversely affecting the threshold of the non-select memory cells. Hereinafter, such a phenomenon will be referred to as substrate disturb. This substrate disturb tends to grow stricter as the flash memory goes larger capacity.
This substrate disturb is explained by taking the ACT type flash memory as an example. First, the principle of operation of the ACT type flash memory is explained based on a memory cell shown in FIG.
19
.
The ACT type flash memory is so constructed that a control gate
1
, an interlayer insulator
2
, a floating gate
3
and a tunnel oxide
4
are formed in layers so as to stretch over a drain
6
and a source
7
provided in a substrate (P-type well)
5
. It is noted that the drain
6
and the source
7
have different donor concentrations. Then, in the program operation in which electrons are pulled out from the floating gate
3
, a negative voltage of −8 V is applied to the control gate
1
and a positive voltage of +5 V is applied to the drain
6
so that the source
7
is put into a floating state, where the electrons are pulled out from the floating gate
3
by the FN tunneling phenomenon. As a result, the threshold of the memory cell to be programmed is lowered to about 1.5 V.
Also, in the erase operation in which electrons are injected into the floating gate
3
, a positive voltage of +10 V is applied to the control gate
1
, a negative voltage of −8 V is applied to the source
7
and a negative voltage of −8 V is applied to the drain
6
, where the electrons are injected into the floating gate
3
by the FN tunneling phenomenon. As a result, the threshold of the cell to be erased is increased so as to rise to about 4 V or more. Like this, the ACT type flash memory is an FN-FN type flash memory.
Further, in the read operation, a voltage of 3 V is applied to the control gate
1
, a voltage of 1 V is applied to the drain
6
and a voltage of 0 V is applied to the source
7
, where a current flowing through the cell is sensed separately by a sense circuit, by which data is read out.
Table 1 lists the applied voltages for the program, erase and read operations.
TABLE 1
Applied voltages in flash memory
Sub-
strate
Control
(P-type
gate
Drain
Source
well)
Program
−8
V
5
V
Open
0
V
Erase
10
V
−8
V
−8
V
−8
V
Read
3
V
1
V
0
V
0
V
Next, for explanation of the substrate disturb at erasing, the erase operation is described in more detail with an array structure shown in FIG.
1
. As schematically shown in
FIG. 1
, the array structure of the ACT type flash memory is a virtual-ground type array structure in which one bit line BL is shared by two memory cells. Then, by sharing the individual bit lines and by using a diffusion layer for sub-bit lines (SBL
0
, SBL
1
, SBL
2
, . . . ), the number of contacts is reduced so that the array area is considerably reduced, thus making it possible to achieve high integration.
It is noted here that BL
0
-BL
4096
are main bit lines, SBL
0
-SBL
4096
are sub-bit lines formed of the diffusion layer (hierarchically different from the main bit lines BL
0
-BL
4096
), and WL
0
-WL
63
are word lines. Also, SG
0
and SG
1
are gate lines of select transistors for selecting a block
1
comprised of word lines WL
0
-WL
31
and block
2
comprised of word lines WL
32
-WL
63
. It is noted that blackened square symbols in the figure represent contact portions between the main bit lines BL and the sub-bit lines SBL. In addition, two sides of the drain and the source to be connected to a sub-bit line SBL common to neighboring memory cells are different in donor concentration from each other.
FIG. 21
schematically shows a cross section of an ACT type flash memory device, where from above to below, a word line (control gate
1
) WL, an interlayer insulator
2
, a floating gate (FG)
3
and a sub-bit line (diffusion layer) SBL are arranged in a layered structure. The sub-bit line SBL provided commonly under end portions of neighboring floating gates
3
,
3
is different in donor concentration between the drain
6
side and the source
7
side.
In the case of the ACT type flash memory having the above constitution, the erase operation is performed on a block-by-block basis. That is, for erasing, in order to raise the threshold of the memory cell, a voltage of +10 V is applied to the word lines WL
0
-WL
31
connecting to the control gate
1
of a select block (block
0
in this case). Further, a voltage of −8 V is applied to the substrate (well)
5
and the main bit lines BL
0
-BL
4096
. In this case, the voltage of the gate line SG
0
is 0 V, making the select transistors on, so that a voltage of −8 V is outputted to the sub-bit lines SBL
0
-SBL
4096
formed of the diffusion layer. As a result, a high electric field is generated between the floating gate
3
and the channel of each memory cell, so that electrons are injected into the floating gate
3
by the FN tunneling phenomenon, with the result that the threshold of the memory cell rises to 4 V or more.
Meanwhile, in a non-select block (block
1
in this case), Vss (0 V) is applied to the word lines WL
32
-WL
63
. Also, −8 V is applied to the gate line SG
1
, making the select transistors off. Accordingly, the sub-bit lines SBL
0
-SBL
4096
connected to the select transistors associated with the gate l
Morrison & Foerster / LLP
Phan Trong
Sharp Kabushiki Kaisha
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