Semiconductor die pad placement and wire bond

Details Semiconductor die pad placement and wire bond Semiconductor die pad placement and wire bond

1998-07-14

2003-11-25

Cao, Phat X. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular signal path connections

C257S203000

Reexamination Certificate

active

06653672

ABSTRACT:

FIELD OF THE INVENTION
The present invention pertains to semiconductor bonding pad placement and wire bonding for semiconductor chip packaging.
BACKGROUND OF THE INVENTION
FIG. 1
shows a first conventional semiconductor die
10
and package
12
. A lead frame
14
has fingers
16
which extend to, but stop short of, the edge of the die
18
. Wire bonds
20
connect conductors on the lead frame
14
to bonding pads
22
on the edge of the die
18
. After encapsulating the die
10
and lead frame fingers
16
in the package
12
, the fingers
16
are cut off the frame
14
.
A shortcoming of a lead frame 14-wire bonding arrangement shown in
FIG. 1
is that the delicate lead frame fingers
16
are not particularly stable when the die
10
is large in comparison to the package. An improved “lead frame over ship” bonding and pad placement is shown in FIG.
2
. As shown, bonding pads
22
are placed away from the edge of the die
24
and are more centrally located on the die
24
. This enables bonding to a lead frame
26
with fingers
28
that extend over the die
24
itself. Because the lead frame fingers
28
are longer, they contact more of the encapsulating plastic of the chip package and therefore are more stable. The improvement in stability is associated with a higher cost since longer, more delicate fingers
28
must be produced on the lead frame
26
, than on the lead frame
14
. Specifically, current lead over chip technology requires that the lead frame be attached to a tape prior to encapsulating the chip and lead frame in a package to provide extra stability to the long, delicate leads. The cost of the tape alone can exceed the cost of certain integrated circuits (such as memories) themselves. Therefore, the pad-placement-wire bonding technique shown in
FIG. 2
is preferably only used for high cost chips that require the added lead frame finger
28
stability associated with the lead frame
26
.
FIG. 3
shows an integrated circuit device
30
. The components of the integrated circuit device
30
can be divided into interface components and functional components. Functional components are those circuits and circuit elements that contribute to the functioning of the integrated circuit device
30
, such as registers, phase-locked loops, storage cells, row and column decoders, precharge circuits, arithmetic logic circuits, clock circuits, analog to digital converters, etc. Interface components are circuits and circuit elements that are provided merely to interface the integrated circuit device
30
to external circuits and to prevent the integrated circuit device
30
from damaging electrical events, such as input buffers, output buffers and ESD protection circuits. Interface components can further be distinguished from functional components by noting that their primary function is to interface the input or output signals between the integrated circuit device
30
and external devices in a protected manner. Interface components otherwise contribute little or nothing to the function to be performed by the integrated circuit device
30
on the input or output signals.
The integrated circuit device
30
has multiple banks, e.g., four banks
31
,
32
,
33
and
34
. Each bank
31
-
34
contains functional components that output signals onto, or receive inputted signals from, (or both output signals onto and receive signals from) one or more conductors
35
. For sake of convenience, these conductors
35
are referred to herein as IO lines although they can be output lines, input lines or both output and input lines. Each IO line
35
is connected at one end to one or more interface components (not shown), wherein at least one of these interface components, in turn, is connected to a bonding pad
36
. In the integrated circuit
30
, the maximum length of IO line
35
over which a signal originating in bank
31
or
34
must propagate is approximately L. However, the maximum length of IO line
35
over which a signal originating in bank
32
or
33
must propagate is approximately 2L, i.e., twice as much. As can be appreciated, this disparity in propagation distance is more pronounced in integrated circuits with more than four banks.
The IO line
35
has a finite impedance and the bonding pad
36
has a finite capacitance C. The resistance experienced by a signal propagating on the IO line
35
is proportional to its length. Thus, signals originating in banks
31
or
34
will be transmitted over a path of IO line
35
having approximately one half of the resistance (and impedance) than signals originating in banks
32
or
33
and transmitted over IO line
35
. As is known, the RC signal propagation delay will therefore be greater (i.e., about twice as long) for signals originating from banks
32
and
33
in comparison to signals originating from banks
31
and
34
. This is undesirable in certain integrated circuits
30
, such as RAMs, ROMs, PALs, PLAs, PROMs, EEPROMs, FPGAs, etc. because the cycle time must be long enough to enable signals to propagate on the longest delay path.
It is an object of the present invention to overcome the disadvantages of the prior art.
SUMMARY OF THE INVENTION
This and other objects is achieved according to the present invention. According to one embodiment, a semiconductor device is provided comprising a die. A first set of plural components, other than interface components, are located on the die surface. A first conductor located on the die surface connects to each component of the first set. A second set of plural components, other than interface components, are located on the die surface. A second conductor located on the die surface connects to each component of the second set. A bonding pad is located on the die surface such that the first set of components lie between the bonding pad and an edge of the die and the second set of components lie between the bonding pad and an opposing edge of the die. The bonding pad receives or transmits one or more signals via the first and second conductors. At least one lead frame finger extends to an edge of the die but does not overlie the die. A bonding wire connects the at least one finger to the bonding pad.


REFERENCES:
patent: 5093712 (1992-03-01), Matsunaga et al.
patent: 5208782 (1993-05-01), Sakuta et al.
patent: 5473198 (1995-12-01), Hagiya et al.
patent: 5604710 (1997-02-01), Tomishima et al.
patent: 5689465 (1997-11-01), Sukegawa et al.
patent: 5742101 (1998-04-01), Sakuta et al.
patent: 5907166 (1999-05-01), Casper et al.

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