Semiconductor integrated circuit device including a clock...

Details Semiconductor integrated circuit device including a clock... Semiconductor integrated circuit device including a clock...

2002-03-04

2003-02-25

Ton, My-Trang Nu (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S143000

Reexamination Certificate

active

06525587

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and, more particularly, to a semiconductor integrated circuit containing a logical processing circuit that is operated to process data in accordance with a distributed clock signal from a clock distribution circuit.
2. Description of the Background Art
FIG. 18
is a diagram schematically showing the entire construction of a conventional integrated circuit (LSI) chip (integrated circuit device). In
FIG. 18
, the LSI chip (semiconductor integrated circuit device) LC includes an analog core circuit AK for processing an analog signal, a digital core circuit DCR for processing a digital signal and an input/output circuit IOK for transmitting and receiving data between the digital core circuit DCR and an external device. Analog core circuit AK includes, for example, a digital/analog conversion circuit and an analog/digital conversion circuit, and externally transmits and receives an analog signal, such as an output signal from a sensor or an image signal.
Digital core circuit DCR includes an internal clock generation circuit CKK for generating an internal clock signal CLKi in accordance with a clock signal CLKe externally supplied, and a digital processing circuit DK for performing a signal processing in a pipeline manner in synchronization with internal clock signal CLKi from internal clock generation circuit CKK. This digital processing circuit DK processes a signal supplied from input/output circuit IOK or analog core circuit AK, and applies the result of processing to the input/output circuit IOK or analog core circuit AK.
Digital processing circuit DK is operated synchronously with internal clock signal CLKi from internal clock generation circuit CKK. In order to operate digital processing circuit DK accurately at high speeds, it is required that internal clock signal CLKi should be transmitted to the respective circuits of digital processing circuit DK at the same phase so that the internal circuits of digital processing circuit DK are operated at the same tiring. In particular, as the scale of the digital processing circuit becomes larger, the interconnection length of the clock signal transfer line becomes longer, and therefore, it is necessary to transmit the internal clock signal to the respective internal circuits without an influence due to a signal propagation delay through the clock signal transfer line.
FIG. 19
is a schematic diagram showing an example of the construction of a conventional digital processing circuit (hereinafter, referred to as a semiconductor integrated circuit). In
FIG. 19
, the semiconductor integrated circuit (DCR)
1
includes a clock buffer
2
for distributing an internal clock signal supplied to an internal clock node
6
to the various parts of the semiconductor integrated circuit, and a logical circuit group RG for carrying out logical processes in synchronization with the internal clock signal from this clock buffer
2
. In
FIG. 19
, one logical circuit
5
, included in the logical circuit group RG, is representatively shown.
Latch circuits
3
and
4
, which complementarily enter through and latch states in synchronization with the internal clock signal that is applied through clock nodes
7
and
8
from dock buffer
2
, are provided in logical circuit
5
. Latch circuit
3
is set to the through state when the internal clock signal applied from clock buffer
2
to clock node
7
goes high, thereby transmitting a signal applied to a data node
9
to logical circuit
5
through a data node
10
. Latch circuit
3
is set to the latch state when the internal clock signal on clock node
7
goes low, thereby isolating data nodes
9
and
10
from each other.
Latch circuit
4
is set to the through state when the internal clock signal on clock node
8
goes low, thereby transmitting the logical processing signal applied to data node
11
from logical circuit
5
to data node
12
. Latch circuit
4
is set to the latch state when the internal clock signal on clock node
8
goes high, thereby isolating data nodes
11
and
12
from each other.
Clock buffer
2
may be an internal clock generation circuit CKK shown in
FIG. 18
, or may carry out a buffering on an internal clock signal from internal clock generation circuit CKK for distributing the resultant clock signal to the logical circuit group RG corresponding to digital processing circuit DK.
Semiconductor integrated circuit
1
is constituted by MOS transistors (insulated gate type field effect transistors). The source node of a P-channel MOS transistor of semiconductor integrated circuit
1
is supplied with a power supply voltage Vdd as a one operating power supply voltage from power supply node
17
through a common source node
13
. Here, the back gate (substrate area) of the P-channel MOS transistor is supplied with power supply voltage Vdd through a common substrate node
14
.
The source of an N-channel MOS transistor that is a component thereof is supplied with a ground voltage (GND; Vss) on a ground node
18
through a common source node
15
, and the back gate (substrate area) of this N-channel MOS transistor is also supplied with the ground voltage of ground node
18
through a common substrate node
16
.
Semiconductor integrated circuit
1
is operated by using both of power supply voltage Vdd of power supply node
17
and the ground voltage (GND) of ground node
18
as operating power supply voltages. Now, a description will be briefly made of the operation of the circuit device.
The clock signal, applied through clock node
6
, is distributed to the each part of semiconductor integrated circuit
1
by clock buffer
2
, and applied to each latch (transfer) circuits such as latch circuits
3
and
4
contained in the logical circuit group RG. Clock buffer
2
, the structure of which will be described later, carries out a buffering on the clock signal and distributes the resultant clock signal such that the propagation delay of the internal clock signal becomes the same in the respective internal parts of integrated circuit
1
.
Latch circuit
3
is set to the through state when the internal clock signal of dock node
7
goes high (logical High level), thereby transmitting the signal on data node
9
to data node
10
. Latch circuit
3
also isolates data node
9
from data node
10
when the internal clock signal on clock node
7
goes low (logical Low level). Thus, latch circuit
3
has a function of holding the state immediately before the internal clock signal on clock node
7
changes from the High level to the Low level.
Logical circuit
5
carries out a predetermined logical process on the signal received through latch circuit
3
, and outputs a signal representing the result of process to data node
11
.
Latch circuit
4
is set to the through state when the internal clock signal, applied from dock buffer
2
to dock node
8
, goes low, thereby transmitting the signal applied on the data node
11
to data node
12
. Latch circuit
4
is also set to the latch state when the internal clock signal on clock node
8
goes high, thereby electrically separating data node
11
and data node
12
.
In other words, when latch circuit
3
is in the through state while latch circuit
4
is in the latch state, logical circuit
5
carries out a logical operation. When the internal dock signals of clock nodes
7
and
8
change to the Low level, latch circuit
3
is set to the latch state to hold data node
10
at the signal state immediately before the change. Thus, there is no change in the logical operation of logical circuit
5
, and the result of logical process appearing on data node
11
is transferred to data node
12
on the subsequent stage. The signal of data node
12
serves as an input signal to a logical circuit or other on a subsequent stage.
One pipeline stage is formed by latch circuits
3
and
4
, and each stage carries out a logical process in synchronization with the internal clock signal from clock buffer
2
. In the logical circuit group RG,

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