Coating apparatus – Gas or vapor deposition
Reexamination Certificate
2000-11-15
2003-12-30
Hassanzadeh, Parviz (Department: 1763)
Coating apparatus
Gas or vapor deposition
C118S712000, C118S695000, C156S345240, C156S345260
Reexamination Certificate
active
06669782
ABSTRACT:
FIELD OF THE INVENTION
The present invention is generally directed to integrated circuits and a process for the formation thereof. More specifically, present invention is directed to the improved performance, reliability, and yield of semiconductor and other related devices by providing material layers having desired functionalities (DF), desired performance (DP), and built in reliability (BIR).
BACKGROUND OF THE INVENTION
The invention of the transistor in 1948 followed by the invention of integrated circuits in 1957 has led to the development of modern microelectronics, which is globally considered as the driver of economic growth. The heart of the modem microelectronics are the silicon integrated circuits or popularly known as silicon chips. Lower cost, high speed, smaller size, and improved reliability of each generation of silicon chips are responsible for the sustained economic growth in the last three decades.
A global examination of the advanced electronic, optical, mechanical, chemical and biological products show that the advances in the field of silicon chip technology have benefited directly or indirectly the manufacturing of other products. As an example of the direct benefit, the success of silicon chip led to the development of the field of solid free form fabrication (SFF) and rapid prototyping (RP). Some details of SFF and RP are described in Chapter 4, “Solid free form fabrication (SFF) and rapid prototyping” of the book, “21
st
Century Manufacturing” pp. 130-170, 2000 by P. K. Wright, which is also incorporated herein by reference. Another example of the direct benefits of silicon chip technology is the development of DNA chips and micro-arrays. Some details of DNA chips and micro-arrays are described in an article and titled “DNA Micro-array (genome Chips)”, by L. Shi, httD://www.gene-chips.com, which is also incorporated herein by reference. Indirectly, the development of improved controllers, high performance robots, information systems as well as improved precision has helped every manufacturing industry. As a specific example of indirect benefits, more and more things that used to be controlled by mechanical or electro-mechanical systems in a closed loop are driven now by silicon chip based microprocessors.
Currently, most advanced silicon chips are using circuits with feature size of 180 nm. At the cost of several billion dollars, the silicon IC industry is currently in the process of switching from 200 mm diameter wafers to 300 mm diameter wafers. Many experts are predicting that in near future, further shrinking of silicon ICs is coming to end. Some of these issues are discussed in an article titled, “The End of the Road for Silicon”, M. Schultz, Nature, vol. 99, pp. 729-730, 1999, which is also incorporated herein by reference.
In order to keep the success of silicon IC industry moving in the 21
st
century, the introduction of new materials, further reduction of the parasitic resistance and capacitance, use of higher aspect ratios of vias and trenches is a necessity. The conventional methods of deposition such as physical vapor deposition have several disadvantages in terms of step coverage, control of stoichiometry of the films and the possibility of selective deposition. Conventional chemical vapor deposition (CVD) techniques also are not suitable for the fabrication of future silicon ICs. As an example, one of the most serious problems concerned with conventional CVD of low resistivity metal films used in the sub-100 nm silicon IC fabrication is the rough surface morphology due to the presence of the large crystal grains. Some of these issues are discussed in an article titled, “Reaction and Film Properties of Selective Properties of Selective Titanium Silicide Low-Pressure Chemical Vapor Deposition”, K. Saito and co-workers, Journal of Electrochemical Society, vol. 141, pp. 1879-1885, 1984, which is also accompanied by reference. Though plasma enhanced CVD has improved surface morphology, the main disadvantage comes in terms of the damage caused to the surface and substrate. Thus, there is a need to invent a CVD technique, which overcomes all of, previously mentioned drawbacks and offers a very low contact resistance.
The manufacturing of sub-70 nm CMOS ICs will also require invention of processing techniques that can provide very high quality junctions. Techniques such as molecular beam epitaxy, and excimer laser annealing for junction formation are being investigated. However, these techniques suffer from severe drawbacks in terms of throughput and defects. Conventionally substrate heating is used during laser crystallization to increase the melt duration and therefore decrease the nucleation rate. This leads to longer processing cycle times and increased manufacturing complexity apart from causing lateral temperature gradients leading to high thermal stress. Also the very high energy density excimer lasers used during the processing beyond the lateral growth regime leads to the roughness at the interface. Small geometry devices are more susceptible to interface roughening as a result of much faster cooling. The use of high energy density lasers also causes blisters on surface. This would not only result in high surface damage, but also degrade device parameters like minority carrier lifetime due to microscopic defects created during the process.
The challenge faced by silicon IC industry is to invent processes land equipment that are capable of providing devices with feature size as small as 1-10 nm using substrates of the diameter in the range of 300 mm and higher. From system point of view, future systems on Chip will have diverse functions (e.g. computing, sensing, imaging, servo mechanics, memory etc.) all integrated on a single chip. These complex systems on chip will be low-cost, ultra small and highly reliable. In order to meet future challenges of silicon IC chips and other related products, the layers of materials grown, deposited or processed on different substrates will have horizontal and or vertical dimensions as small as 1 nm. These different layers of materials either patterned by lithography or written directly will be used in the development of chips having components of the order of millions to billions with diverse functionalities. Due to the chip complexity, testing of such chips may be more expansive than the manufacturing cost. Some of these issues for developing future systems on chip are described in an article and titled, “Current reliability issues and future technologies for systems on silicon-process, circuits, chip architecture, and design”, Takeda et al, Microelectronics and Reliability, Vol. 40, pp. 897-908, 2000, which is also incorporated herein by reference.
In future, a single layer of material will have to perform more than one function. As an example, the gate material used in the fabrication of metal-insulator field effect transistor (MISFET) will have to provide appropriate work function as well as a barrier against the transportation of any type of defects or flaws (microscopic as well as macroscopic) into the gate dielectric material.
In the fabrication of micro-electromechanical systems (MEMS), stiction and wear are two major problems. Some of these issues of MEMS are described an article and titled, “Effect of W Coating on Microengine Performance”, Mami et al., Proc. 2000 IEEE international reliability Physics Symposium Proc. pp. 146-151, 2000, which is also incorporated herein by reference. The reduction of micro-roughness at each surface and interface as well as reduction of stress can improve the performance and reliability of all MEMS products.
Devices based on magnetic materials such as hard disk storage, magnetic static random access memory (MRAM) etc. also need defect free, and stoichiometric films. Some of the materials used in the magnetic devices are usually a few nanometer thick, as described in an article, “Read-Write Heads,” J. Baliga, Semiconductor International, vol. 23 (10), pp. 95-102, 2000, which is also incorporated herein by reference.
Thermal processing is an integral part in
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