Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2002-07-18
2003-11-25
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185110, C365S185130, C365S063000
Reexamination Certificate
active
06654282
ABSTRACT:
Japanese Patent Application No. 2001-221788 filed on Jul. 23, 2001, is hereby incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device including memory cells, each having two nonvolatile memory elements controlled by one word gate and two control gates.
As one type of nonvolatile semiconductor memory device, a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor or -Substrate) device is known. In the MONOS nonvolatile semiconductor memory device, a gate-insulating layer between a channel and a gate is formed of a laminate consisting of a silicon oxide film, silicon nitride film, and silicon oxide film. Charges are trapped in the silicon nitride film.
The MONOS nonvolatile semiconductor memory device is disclosed in the literature (Y. Hayashi, et al., 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 122 to 123). This literature discloses a MONOS flash memory cell including two nonvolatile memory elements (MONOS memory cells) controlled by one word gate and two control gates. Specifically, one flash memory cell has two charge trap sites. A memory cell array region is formed by arranging a plurality of MONOS flash memory cells having such a structure in the row direction and the column direction.
BRIEF SUMMARY OF THE INVENTION
The present invention may provide a nonvolatile semiconductor memory device enabling contact sections for connecting bit lines to be easily formed and capable of decreasing the resistance of the control gates.
One aspect of the present invention relates to a nonvolatile semiconductor memory device comprising a memory cell array region in which a plurality of memory cells are arranged in a first direction and a second direction intersecting each other, each of the memory cells having first and second nonvolatile memory elements and being controlled by one word gate and first and second control gates.
A plurality of bit lines extending in the first direction, each of the bit lines being connected with the memory cells arranged in the first direction are provided.
The first control gate and the second control gate adjacent each other in the second direction are respectively formed on one side and the other side of each of the plurality of bit lines. Ends of the first and second control gates formed on the one side and the other side of each of the plurality of bit lines are respectively connected by two continuous sections. This enables to reduce the resistance of the control gates by approximately fifty percent in comparison with the case where only one end of each of the first and second control gates is connected with each other by one continuous section.
Each of the plurality of bit lines has a projecting section in which one end portion thereof projects in the first direction outside an end of an adjacent bit line among the bit lines arranged in the second direction. The projecting section has a large-width region having a width greater than a width of each of the bit lines in a region in which the plurality of memory cells are formed. Therefore, contact sections for drawing the bit lines are easily formed in the projecting sections.
In the one aspect of the present invention, end portions of even-numbered bit lines among the plurality of bit lines, on one side, may project in the first direction outside ends of odd-numbered bit lines among the plurality of bit lines, on the one side; and end portions of the odd-numbered bit lines, on an opposite side to the one side, may project in the first direction outside ends of the even-numbered bit lines, on the opposite side. This enables the degree of integration of the memory cells to be increased as described later.
In the one aspect of the present invention, the memory cell array region may comprise a plurality of block regions formed by dividing the memory cell array region in the first direction, each of the block regions having the memory cells. Each of the plurality of block regions may be provided with a plurality of sub bit lines extending in the first direction and may be connected with the memory cells, respectively; and a plurality of main bit lines may be formed extending across the plurality of block regions in the first direction, each of the main bit lines being connected in common with the plurality of sub bit lines which are respectively formed in the plurality of block regions arranged in the first direction.
The first control gate and the second control gate may be formed on one side and the other side of each of the plurality of sub bit lines, respectively. Ends of the first and second control gates formed on the one side and the other side of each of the plurality of sub bit lines may respectively be connected by two continuous sections.
Each of the plurality of sub bit lines may have a projecting section in which one of the end portions projects in the first direction outside an end of an adjacent sub bit line among the sub bit lines arranged in the second direction. The projecting section may have a large-width region having a width greater than a width of each of the sub bit lines in a region in which the plurality of memory cells are formed.
In one aspect of the present invention, end portions of even-numbered sub bit lines among the plurality of sub bit lines, on one side, may project in the first direction outside ends of odd-numbered sub bit lines among the plurality of sub bit lines, on the one side; and end portions of the odd-numbered sub bit lines, on an opposite side to the one side, may project in the first direction outside ends of the even-numbered sub bit lines, on the opposite side. This enables the degree of integration of the memory cells to be increased for reasons described later.
In the one aspect of the present invention, the plurality of sub bit lines disposed in two of the block regions adjacent in the first direction may include first sub bit lines which are disposed in one of the two block regions and second sub bit lines which are disposed in the other of the two block regions, one of the first sub bit lines and one of the second sub bit lines being connected with the same one of main bit lines and respectively having projecting sections facing each other.
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Mai Son
Seiko Epson Corporation
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