Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2003-01-21
2003-11-04
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185190, C365S185220, C365S185280, C365S185240, C365S185330
Reexamination Certificate
active
06643177
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a non-volatile memory. Specifically, the present invention relates to a method for programming a flash memory device with a dynamic reference array.
BACKGROUND ART
Many electronic devices, such as computers, personal digital assistants, cellular telephones, digital cameras and similar systems and devices include processors and memory. The memory is used to store computer programs to be executed by the device and/or data operated on by the processors to achieve the functionality of the device. Many devices and systems require that this information be retained in permanent storage
on-volatile medium so that tile data and computer programs is not lost when power is removed.
Flash memory is an example of a non-volatile memory device. Flash memory devices use a memory cell transistor that is similar to a metal-oxide semiconductor field effect transistor (MOSFET) with an additional floating gate structure disposed in the insulating layer between the control gate, and the source and drain. The channel between the source and drain is separated from the floating gate by a thin dielectric layer.
Programming of a memory cell is done by applying the appropriate potentials to the control gate, source, and drain so that electrons are transferred to the floating gate through the thin dielectric layer. The addition of electrons to the floating gate increases the threshold voltage for the transistor above the value for an uncharged floating gate. Two techniques used for electron transfer across the dielectric layer are channel hot electron (CHE) and Fowler-Nordheim tunneling.
A read operation is performed by biasing the source and drain while applying a read voltage that is above the threshold voltage (V
t
) for an unprogrammed cell and below the threshold voltage for a programmed cell. An unprogrammed cell will conduct current at the applied read voltage, and thus may represent a logical “1”, whereas a programmed cell will not conduct, and may represent a logical “0.”The erasure of a memory cell is carried out by applying potentials to the control gate, source, and drain so that electrons are removed from the floating gate, thus lowering the threshold voltage.
Conventional flash memory devices utilize transistors that store a single bit per transistor and have a floating gate that is a conductor, such as polysilicon. Multi-bit memory cells have been developed that allow for storing more than one bit per transistor. These transistors may use a single floating gate with multiple programming levels, a split floating gate to provide more than one charge storage site, or a dielectric layer (in place of a floating gate) in which charge may be locally stored in multiple sites.
An example of a dielectric layer used for charge storage is a composite ONO layer (silicon nitride sandwiched between two layers of silicon dioxide). This layer may be used in a dual-bit memory cell that can store two bits per cell; however, the aging and cycling characteristics of the ONO layer are different from the conventional polysilicon floating gate.
When used for charge storage in a memory cell, an ONO layer may develop an increase in charge loss with cycling, giving rise to different I-V characteristics at the end of life as compared to the I-V characteristics at the beginning of life for the device. In order to accommodate the changing I-V characteristics in the read operation, a dynamic reference array may be used in place of a static reference.
A dynamic reference array includes a set of memory cells that are programmed and erased along with the core memory cells of a flash memory device. Thus, the aging associated with the ONO layer essentially becomes a common mode error that can be canceled out by being introduced at both inputs of the comparator used in the read operation. As the V
t
distributions shift for the programmed states of the memory cell, the reference levels shift as well, allowing the reference to remain centered between the programmed states.
Although the dynamic reference array can be used to adjust the reference voltage used for determining the programmed state of a memory cell, there is still the problem of reduced read margin that may occur. For example, the threshold voltages associated with two programmed states may decrease over time, with a concomitant decrease in the separation between the V
t
distributions of the two programmed states. This decreased separation reduces the margin for error in the read operation. In the worst case of overlapping distributions, the read operation cannot be performed reliably.
DISCLOSURE OF THE INVENTION
A method for providing a modified threshold voltage distribution for a dynamic reference array in a flash memory cell array is disclosed. The dynamic reference array and an associated core memory cell array are programmed using two different programming processes to produce different V
t
distributions for the dynamic reference array and the core memory cell array. The dynamic reference array is programmed using a finer program pulse to achieve a smaller distribution width, thus enhancing the read margin for the memory cell array.
In an embodiment of the present invention, a first programming pulse is used to program a core memory cell in a memory cell array. The pulse is applied using a program/verify cycle. A reference cell in the memory cell array is also programmed with a program/verify cycle, using a second pulse having a shorter duration than the first. The programming of core memory cells and their associated reference cells may be repeated for a number of cells. The shorter duration of the programming pulse used for the reference cells results in a smaller standard deviation in the reference cell V
t
distribution, as compared to the core cell V
t
distribution, thus improving the read margin.
In another embodiment of the present invention, a first programming pulse is used to program a core memory cell in a memory cell array. The pulse is applied using a program/verify cycle. A reference cell in the memory cell array is also programmed with a program/verify cycle, using a second pulse having a smaller amplitude than the first. The programming of core memory cells and their associated reference cells may be repeated for a number of cells. The smaller amplitude of the programming pulse used for the reference cells results in a smaller standard deviation in the reference cell V
t
distribution, as compared to the core cell V
t
distribution, thus improving the read margin.
REFERENCES:
patent: 6519184 (2003-02-01), Tanaka et al.
Chen Pau-Ling
Le Binh Quang
Advanced Micro Devices , Inc.
Tran Andrew Q.
Wagner , Murabito & Hao LLP
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