Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
2001-01-17
2003-02-18
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C438S118000, C438S465000
Reexamination Certificate
active
06521485
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a wafer level chip size package (WLCSP) and, in particular, to a method for manufacturing a wafer level chip size package having lead frame with redistribution lead fingers and using drilling and filling, instead of wire bonding or bumps, for inner electrical connection.
2. Description of the Prior Art
Packages in the same size of, or slightly larger than the chips they pack are always called chip size package, CSP. The size of the package is not larger than 1.2 times of size of the chip and meets the recent demand of electronic component being thin and small. Comparing to both bare chip and flip chip, chip size package has better protection to resist dust and humidity.
To simplify manufacturing process of chip size package, a wafer package is claimed in EP patent No.0844665. A lead frame is used as interposer of the chip size package and process of packaging proceeds directly on a wafer having a plurality of chips. For the out connecters of lead frame can only being formed on the perimeter of the chip, therefore, there is no way this method can pack wafer having multi-electrodes. And, for using bonding wire as inner connector between lead frame and chip by wire bonding, wire bonding machine in the back process has to be moved to wafer process on the pre process, and that is not proper for process integration.
A well-known method for wafer level package in accordance with U.S. Pat. No. 6,022,738 discloses a technique to drill blind hole on the isolative package body of the pre-sealed wafer, and provide metal coating traversing the package body for plating solder bumps. The drawback is that the wafer has to place redistribution circuits and place the connecting pads in a proper position, so that the method for wafer package cannot be applied in a wafer having different distribution of connecting pads.
SUMMARY OF THE INVENTION
Therefore, the first object of present invention is to provide a method for manufacturing the wafer level chip size package which package on the wafer directly, in particular, directly package on wafer having different type of connecting pads distribution or multi-electrodes.
The second object of present invention is to provide a method for manufacturing the wafer level chip size package, which selectively etch the first layer of a metal plate to form the redistribution conductive circuits, drill blind holes after securing metal and wafer, and electrically connect connecting pads of wafer and conductive circuits of metal plate by filling conductive material into blind holes, thus chip size packages having multi-electrodes can be produced.
The third object of present invention is to provide a chip size package, wherein, the redistribution conductive circuits of the chip size package having the first ends and the second ends, wherein, the first ends being at vertical position with connecting pads of chip, and acting as inner electrical connection of the package structure to replace bumps or bonding wire by drilling and traversing the first ends after encapsulating.
The forth object of present invention is to provide a method to grow bumps on wafer, wherein proceed packaging wafer with metal plate (lead frame) and redistribute out connecting points simultaneously, thus can package wafer having different connecting pads and eliminate process of redistribution in wafer.
According to the method for manufacturing a wafer level chip size package, the steps of the method comprises:
providing a wafer having a plurality of chips, each chip having a plurality of connecting pads on its active surface;
providing a metal plate consisting of the first layer and the second layer, wherein, a plurality of conductive circuits being formed by selectively etching the first layer of the metal plate, the plurality of conductive circuits being fixed on the second layer of the metal plate, and individual conductive circuit having at least the first end and the second end, and the first ends corresponding to the distribution of connecting pads of chips in the wafer;
securing active surface of the wafer to the first layer of the metal plate, when the wafer and the metal plate being secured, connecting pads of the chips and the first ends of the conductive circuits being in vertical position to each other;
drilling blind holes on the plurality of first ends, wherein the blind holes traversing through metal plate and expose connecting pads of the wafer;
filling conductive material on the plurality of blind holes until the connecting pads of chip and the first ends of the conductive circuits becoming electrical connection;
removing the second layer of the metal plate;
planting solder balls on the second ends of the conductive circuits; and
dicing the packed wafer and resulting in a plurality of chip size packages.
REFERENCES:
patent: 4052787 (1977-10-01), Shaheen et al.
patent: 5411918 (1995-05-01), Keible et al.
patent: 5742094 (1998-04-01), Ting
patent: 6022758 (2000-02-01), Badehi
patent: 6153448 (2000-11-01), Takahashi et al.
patent: 6309912 (2001-10-01), Chiou et al.
patent: 6316289 (2001-11-01), Chung
patent: 6333469 (2001-12-01), Inoue et al.
patent: 0844665 (1998-05-01), None
Chao-Chia Chang
Chen Allen
Chen Captain
Chien-Tsun Lin
Hsia Kevin
Estrada Michelle
Walsin Advanced Electronics LTD
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