Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-08-22
2003-12-02
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185110
Reexamination Certificate
active
06657899
ABSTRACT:
BACKGROUND OF THE INVENTION
Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory. One type is RAM (random-access memory). This is typically used as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to ROM, which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. Like other types of ROM, EEPROM is traditionally not as fast as RAM. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. Many modern PCS have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in modems because it enables the modem manufacturer to support new protocols as they become standardized.
A typical Flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge in the floating gate.
A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higher clock speeds than conventional DRAM memory. SDRAM synchronizes itself with a CPU's bus and is capable of running at 100 MHZ, about three times faster than conventional FPM (Fast Page Mode) RAM, and about twice as fast EDO (Extended Data Output) DRAM and BEDO (Burst Extended Data Output) DRAM. SDRAM's can be accessed quickly, but are volatile. Many computer systems are designed to operate using SDRAM, but would benefit from non-volatile memory.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a non-volatile memory device that can operate in a manner similar to SDRAM operation. Further, there is a need for a synchronous memory that can provide multiple status reading options.
SUMMARY OF THE INVENTION
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a method of operating a memory device comprises initiating a write operation on a first block of an array of memory cells, initiating a first read operation on the first block during the write operation, and automatically outputting a write status in response to initiating the first read operation. The write status indicates that the write operation is being performed on the first block.
In another embodiment, a method of controlling a memory device comprises executing a write operation on a first addressable block of an array of memory cells, and setting a bank register to a first state while the write operation is being performed. The first state indicates that the first block is being written to. The method further comprises initiating a first read operation in response to a read command received during execution of the write operation, comparing a read address provided with the read command to the bank register, and automatically outputting a write status in response to the read command if the read address is located in the first block. The write status indicates that the write operation is being performed on the first block.
In yet another embodiment, a method of controlling a memory device comprises coupling a write command, a write address and write data from a first processor to the memory device, and executing a write operation on a first addressable block of an array of memory cells. The first addressable block corresponds to the write address. A bank register is set to a first state while the write operation is being executed, wherein the first state indicates that the first block is being written to. The method includes coupling a read command and a read address from a second processor to the memory device, initiating a first read operation in response to a read command received during execution of the write operation, comparing the read address provided with the read command to the bank register, and automatically outputting a write status in response to the read command if the read address corresponds to the first block. Again, the write status indicates that the write operation is being executed on the first block.
A memory device is provided in one embodiment that comprises an array of memory cells arranged in a plurality of addressable blocks, a bank register having a plurality of bits corresponding to the plurality of blocks, and an array status register to store status data indicating where a write operation is performed on the array. Control circuitry is provided to perform a write operation on a first block of the plurality of blocks and automatically couple the status data to external data connections in response to a read command.
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Le Vu A.
Leffert Jay & Polglaze P.A.
Micro)n Technology, Inc.
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