Input circuit

Details Input circuit Input circuit

2002-03-21

2003-11-04

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S057000

Reexamination Certificate

active

06642748

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an input circuit, and more particular to an input circuit used for receiving signals exchanged among different semiconductor integrated circuits.
2. Description of the Prior Art
In general, this type of input circuit is used in transferring signals through bus lines or transmission cables interconnecting different integrated circuits. The input circuit receives signals and propagates the signal information to its own semiconductor integrated circuit. Therefore, without exception, every input circuit has a data input terminal for receiving signals from other integrated circuits and a data output terminal for propagating signal information to its own integrated circuit.
In recent years, as data transfer rate has been increased, it has come to be general that signals transferred among integrated circuits are low-amplitude signals on the order of 100 mV to 400 mV in spite that the power-source voltage of each integrated circuit is in the range of the order of 2 V to 5 V. Furthermore, in order to improve the reliability of logic signals, the differential-signal transmission system has come to be used instead of the single-ended signal transmission system that was the main system used formally. The differential-signal transmission system recognizes the difference of the amplitudes of two single-ended signals that are transferred simultaneously, thereby improving noise margins and reducing electromagnetic interference, and it is frequently used where fast and high-reliability processing is required.
Therefore, to support this type of transmission system, input circuits must provide functions of receiving differential signals and amplifying the voltages of low-amplitude data signals to voltages equal to or near the power-source voltages of their own integrated circuits.
Clock-triggered data processing methods, in which clock signals are used as triggers, are widely employed in integrated circuits to avoid loss of information due to data signal conflicts or time-varying factors in performing operations on the information propagated from the input circuits. A flip-flop circuit is known as a typical circuit of the clock-triggered type, which receives clock and data signals and temporarily stores the data in response to the transition timing of the clock signal.
FIG. 4
shows an exemplary data processing operation when the prior-art input circuit is connected to a flip-flop circuit.
Referring to
FIG. 4
, reference numeral
49
indicates an input circuit, and reference numeral
50
indicates a flip-flop circuit. Input data signal DIN input to the input circuit
49
is a low-amplitude signal, and data signal DOUT output from the input circuit
49
is generally a signal with an amplitude equal to the power-source voltage. The output terminal of the input circuit
49
is connected to the data input terminal D of the flip-flop circuit
50
. The flip-flop circuit
50
is equipped with a clock terminal (CK), the data input terminal (D), and a data output terminal (Q). The clock terminal CK receives a clock signal CK, and the data input terminal receives a data signal DOUT.
In
FIG. 4
, the input circuit
49
amplifies the input data signal DIN from its low amplitude to an amplitude near the amplitude (on the order of 2 V to 5 V) of the power-source voltage of the integrated circuit, and provides the amplified input data signal to the data input terminal (D) of the flip-flop circuit
50
, which is an internal circuit. As shown in
FIG. 5
, the flip-flop circuit
50
latches the data signal DOUT in response to the rising transition of the clock signal CK, stores it temporarily, and outputs an output signal Q, also in response to the clock transition. At this time, the relative timing relationship between the clock signal CK and data signal DOUT for enabling normal operations of the flip-flop circuit
50
must satisfy a minimum setup time requirement Tsu and hold time requirement Th, so the phase of the clock signal CK is adjusted to satisfy these requirements.
The example of prior art shown in
FIG. 4
, however, presents two major problems. One of the problems is that the signal amplitude amplification operation of the input circuit
49
lacks speed, so it cannot support fast transmission rates, such as rates of several gigabits per second (Gbps). The other problem is that the input circuit
49
and the flip-flop circuit
50
are configured separately, so it is impossible to keep the delay time of the data signal DOUT of the input circuit
49
constant with respect to the clock signal CK in the process of supplying the output signal DOUT to the flip-flop circuit
50
, making it difficult to keep the setup time Tsu and hold time Th within the range enabling normal operations of the flip-flop circuit
50
.
FIG. 6
shows a prior-art input circuit that has been devised to solve these problems.
Referring to
FIG. 6
, reference numerals
1
to
4
indicate PMOS transistors, and reference numerals
5
to
11
indicate NMOS transistors. The source of the PMOS transistor
1
is connected to the power source (VDD), and the drain of the PMOS transistor
1
is connected to the drain of the NMOS transistor
5
. Given that the source of the NMOS transistor
5
is kept at the ground potential, the PMOS transistor
1
and NMOS transistor
5
form a CMOS inverter having a noninverting output terminal Z and an inverting output terminal ZB as its input and output nodes, respectively. On the other hand, given that the source of the NMOS transistor
6
is kept at the ground potential, the PMOS transistor
2
and the NMOS transistor
5
form a CMOS inverter having an inverting output terminal ZB and a noninverting output terminal Z as its input and output nodes. This cross-couples the input and output nodes of the CMOS inverter consisting of the PMOS transistor
1
and NMOS transistor
5
with the input and output nodes of an CMOS inverter consisting of the PMOS transistor
2
and NMOS transistor
6
, thereby forming a flip-flop circuit.
The source of a PMOS transistor
3
is connected to the power source (VDD); its drain is connected in common to the gates of both the PMOS transistor
1
and NMOS transistor
5
; and its gate receives a clock signal CK
1
. The gates of the PMOS transistor
1
and NMOS transistor
5
and the drain of the PMOS transistor
3
are connected to the noninverting output terminal Z. The source of the PMOS transistor
4
is connected to the power source (VDD); its drain is connected in common to the gates of the PMOS transistor
2
and NMOS transistor
6
; and its gate receives a clock signal CK
1
. The gates of both the PMOS transistor
2
and NMOS transistor
6
and the drain of the PMOS transistor
4
are connected to the inverting output terminal ZB.
The drains of the NMOS transistors
7
and
8
are connected to the sources of the NMOS transistors
5
and
6
mentioned above, respectively, and the sources of the NMOS transistors
7
and
8
are connected to ground (GND) through the NMOS transistor
9
. The gates of the NMOS transistors
7
and
8
are connected to the noninverting data terminal D and inverting data terminal DB, respectively, and the gate of the NMOS transistor
9
receives a clock signal CK
1
. The drain of the NMOS transistor
10
is connected to the source of the NMOS transistor
5
and the drain of the NMOS transistor
7
, and its source is connected to ground (GND). In contrast, the drain of the NMOS transistor
11
is connected to the source of the NMOS transistor
6
and the drain of the NMOS transistor
8
, and the source of the NMOS transistor
11
is connected to ground (GND). The gates of NMOS transistors
10
and
11
receive a clock signal CK
2
.
Next, the operation of the flip-flop circuit shown in
FIG. 6
will be described.
Referring to the timing diagram shown in
FIG. 7
, at time t=0, clock signal CK
1
is at the low logic level while the noninverting output terminal Z and inverting output terminal ZB are at the high logic level. Next, when clock signal CK
1
ch

Affiliated with

Also associated with

Rating

Input circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Input circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Input circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3178979