Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2003-01-13
2003-12-16
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S425000, C438S431000
Reexamination Certificate
active
06664170
ABSTRACT:
BACKGROUND
1. Technical Field
The present disclosure relates to a method for forming a device isolation layer of a semiconductor device, and more particularly, to a method for forming a device isolation layer of a semiconductor device capable of suppressing a hump and an electric field concentration effect by preventing the generation of a remote effect at an edge of the device isolation layer wherein the profile of the device isolation layer is implanted in a silicon substrate by a shallow trench isolation (STI) process.
2. Description of the Related Art
Generally, in order to fabricate devices such as a transistor, a capacitor or the like in a silicon substrate, an isolation region is formed to prevent the device from electrically connecting to an active area capable of flowing an electric current and isolate the devices from each other.
Thus, recently a shallow trench isolation (STI) process has been widely used for forming a device isolation region in a semiconductor device. The STI region is generally formed as follows; a trench having a predetermined depth is formed on the silicon substrate; an oxide layer is deposited onto the trench; and an undesired portion of the oxide layer is etched by using a chemical mechanical polishing (CMP) process.
FIGS. 1
a
-
1
d
are cross-sectional views sequentially showing a method for forming a device isolation layer of a semiconductor device in accordance with a prior art method.
FIG. 2
is a cross-sectional view showing shortcomings of a device isolation layer formed in accordance with a conventional manufacturing method.
As shown in
FIG. 1
a
, a pad oxide layer
2
is formed on a silicon substrate
1
with a predetermined thickness to insulate and a nitride layer
3
is formed on the pad oxide layer
2
to protect between an upper and a lower layer.
At this time, the nitride layer
3
can be used as an etching mask during the trench etching process or can be used for an etching stop layer during a later CMP process.
After a photoresist layer is coated on top of the nitride layer
3
, the photoresist layer is patterned into a photoresist pattern (not shown) by a lithography process, a device isolation region is exposed on the silicon substrate
1
by etching the nitride layer
3
and the pad oxide layer
2
using the photoresist pattern as a mask sequentially.
Then, after removing the photoresist pattern (not shown), a trench
4
is formed in the silicon substrate
1
by performing a dry etching using the nitride layer
3
as an etching mask.
Thereafter, as shown in
FIG. 1
b
, a gap filling oxide layer
5
is deposited on the resultant structure by using a chemical vapor deposition method, at this time, a step is formed in the gap filling oxide layer
5
deposited between the device isolation region and the active region due to the trench formed in the silicon substrate
1
.
As shown in
FIG. 1
c
, the step between the device isolation region and the active region is alleviated by partially etching the gap filling oxide layer
5
in the active region by depositing a photoresist layer
6
on the top of the gap filling oxide layer
5
of the device isolation region.
As shown in
FIG. 1
d
, after the resultant structure is planarized by grinding the structure onto a top of a nitride layer (not shown) by a chemical mechanical polishing process, the device isolation layer is formed by removing the nitride layer (not shown).
However, if the conventional method for forming the device isolation layer as described above is utilized, since a dry etching is performed by the photoresist pattern as a mask to reduce the step between the device isolation region and the active region, the position of the photoresist pattern becomes misaligned, resulting in damage to the active region by etching the active region as shown in
FIG. 2
, which, in turn, deteriorates the characteristics and reliability of the semiconductor device.
In addition, during the removal of the nitride layer, an over etching is performed to completely remove the nitride layer. At this time, an electrical fringing field generates an edge portion of the device isolation layer during the operation of the device by forming a moat at an edge portion of the device isolation layer with etching the gap filling oxide layer and the nitride layer at a different etching ratio. Consequently, the device deteriorates in electrical as well as a threshold voltage when changed by the hump.
SUMMARY OF THE DISCLOSURE
The disclosure provides a method for forming a device isolation layer of a semiconductor device capable of preventing loss of an active region due to a misalignment of a photoresist pattern by alleviating a step between the active region and the device isolation region by using a photoresist layer containing silicon during a line etching of the active region for alleviating the step between the active region and the device isolation region when a gap filling oxide layer is planarized by a shallow trench isolation (STI) process.
A method for forming a device isolation layer of a semiconductor device in accordance with the disclosure comprises the steps of: providing a silicon substrate having a substructure of a predetermined configuration; depositing a nitride layer on a top of the silicon substrate; forming a trench on a device isolation region of the silicon substrate; depositing a gap filling oxide layer on the trench and a portion of the silicon substrate which does not form the trench; forming a photoresist pattern on the gap filling oxide layer of the device isolation region; oxidizing the photoresist pattern by performing a first oxidation process; removing a portion of the gap filling oxide layer by using the oxidized photoresist pattern as a mask to form a first intermediate structure; planarizing the first intermediate structure to a top of the nitride layer by using a chemical mechanical polishing process; removing the nitride layer to form a second intermediate structure; forming an amorphous silicon layer on top of the second intermediate structure; etching the front of the amorphous silicon layer to form an amorphous silicon spacer on a side wall of an extruded field oxide layer; and oxidizing the spacer by performing a second oxidation process.
The photoresist pattern containing 7% silicon to 50% silicon is deposited at a thickness of 500 Å to 15000 Å. The oxidation process for oxidizing the surface of the photoresist pattern is performed by plasma ashing using O
2
plasma at a temperature ranging from 50° C. to 200° C. or an ion implantation method for implanting O
2
ions in order to prevent damage to the active region due to misalignment of the photoresist pattern.
The amorphous silicon layer is formed at a thickness ranging from 300 Å to 700 Å at a temperature of 400° C. to 600° C. by using a low chemical vapor deposition method. The spacer is oxidized by O
2
plasma treatment at a temperature of 200° C. to 800° C. to increase the width of the gap filling oxide layer on the upper portion of the active region and prevent the moat phenomenon.
REFERENCES:
patent: 3997367 (1976-12-01), Yau
patent: 5960298 (1999-09-01), Kim
patent: 5966615 (1999-10-01), Fazan et al.
patent: 6183937 (2001-02-01), Tsai et al.
patent: 6207541 (2001-03-01), Das et al.
patent: 6372604 (2002-04-01), Sakai et al.
Davari et al., “A new planarizatoin technique, using a combination of RIE and chemical Mechanical polish (CMP),”International Electron Devices Meeting, Technical Digest(IEEE), pp. 61-64, (Dec. 3-6, 1989).
Fazan et al., “A highly manufacturable trench isolation process for deep submicron DRAMs,”International Electron Devices Meeting, Technical Digest(IEEE), pp. 57-60, (Dec. 5-8, 1993).
Hynix / Semiconductor Inc.
Marshall & Gerstein & Borun LLP
Quach T. N.
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