Semiconductor device structure and method for forming

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S424000, C438S425000, C438S426000, C257S510000, C257S513000

Reexamination Certificate

active

06518146

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to a semiconductor device structure and more specifically to trench isolation structures.
RELATED ART
The ability to integrate a wider variety of devices and structures into a single integrated circuit allows for increased speed and efficiency while reducing costs. However, problems arise during the integration of these different devices and structures. For example, some integrated circuits require multiple types of shallow trench isolation having different properties. An embedded non-volatile memory (NVM), for example, requires good trench corner rounding for bitcell reliability, endurance, and uniform program/erase threshold voltage distribution. However, logic devices located within a same integrated circuit as the NVM require narrower trenches but with less severe corner rounding as compared to the trenches within the embedded NVM. Filling of these narrower trenches, though, may result in voids, thus limiting the yield of the integrated circuit. Therefore, a need exists for the formation of semiconductor device structures within an integrated circuit having different isolation properties and requirements.


REFERENCES:
patent: 5395780 (1995-03-01), Hwang
patent: 5438016 (1995-08-01), Figura et al.
patent: 5472904 (1995-12-01), Figura et al.
patent: 5605848 (1997-02-01), Ngaoaram
patent: 5646063 (1997-07-01), Mehta et al.
patent: 5683946 (1997-11-01), Lu et al.
patent: 5712208 (1998-01-01), Tseng et al.
patent: 5726087 (1998-03-01), Tseng et al.
patent: 5753962 (1998-05-01), Jeng
patent: 5837596 (1998-11-01), Figura et al.
patent: 6093659 (2000-07-01), Grider et al.
K.V. Rao et al., “Trench Capacitor Design Issues In VLSI DRAM Cells”, 1986 IEEE, Section 6, 4 pgs.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Semiconductor device structure and method for forming does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device structure and method for forming, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device structure and method for forming will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3172589

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.