Semiconductor wafer for improved chemical-mechanical...

Details Semiconductor wafer for improved chemical-mechanical... Semiconductor wafer for improved chemical-mechanical...

1999-11-12

2003-10-14

Nadav, Ori (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C438S692000, C438S697000, C438S633000

Reexamination Certificate

active

06633084

ABSTRACT:

TECHNICAL FIELD
The present invention relates to chemical-mechanical polishing of semiconductor wafers that have large area features; more particularly, the present invention relates to a semiconductor wafer that reduces dishing caused by chemical-mechanical polishing over large area features.
BACKGROUND OF THE INVENTION
Chemical-mechanical polishing (“CMP”) processes remove materials from the surface layer of a wafer in the production of ultra-high density integrated circuits. In a typical CMP process, a wafer presses against a polishing pad in the presence of a slurry under controlled chemical, pressure, velocity, and temperature conditions. The solution has abrasive particles that abrade the surface of the wafer, and chemicals that oxidize and/or etch the surface of the wafer. Thus, when relative motion is imparted between the wafer and the pad, material is removed from the surface of the wafer by the abrasive particles (mechanical removal) and by the chemicals (chemical removal) in the slurry.
FIG. 1
schematically illustrates a conventional CMP machine
10
with a platen
20
, a wafer carrier
30
, a polishing pad
40
, and a slurry
44
on the polishing pad. The platen
20
has a surface
22
to which an under-pad
25
is attached, and the polishing pad
40
is positioned on the under-pad
25
. The under-pad
25
protects the platen
20
from caustic chemicals in the slurry
44
and from abrasive particles in both the polishing pad
40
and the slurry
44
. In conventional CMP machines, a drive assembly
26
rotates the platen
20
as indicated by arrow A. In another, type of existing CMP machine, the drive assembly
26
reciprocates the platen back and forth as indicated by arrow B. The motion of the platen
20
is imparted to the pad
40
because the polishing pad
40
frictionally engages the under-pad
25
. The wafer carrier
30
has a lower surface
32
to which a wafer
12
may be attached, or the wafer
12
may be attached to a resilient pad
34
positioned between the wafer
12
and the lower surface
32
. The wafer carrier
30
may be a weighted, free-floating wafer carrier, or an actuator assembly
36
may be attached to the wafer carrier
30
to impart axial and rotational motion, as indicated by arrows C and D, respectively.
In the operation of the conventional polisher
10
, the wafer
12
is positioned face-downward against the polishing pad
40
, and then the platen
20
and the wafer carrier
30
move relative to one another. As the face of the wafer
12
moves across the polishing surface
42
of the polishing pad
40
, the polishing pad
40
and the slurry
44
remove material from the wafer
12
.
CMP processes must consistently and accurately produce a uniform, planar surface on the wafer because it is important to accurately focus circuit patterns on the wafer. As the density of integrated circuits increases, current lithographic techniques must accurately focus the critical dimensions of photo-patters to within a tolerance of approximately 0.35-0.5 &mgr;m. Focusing the photo-patterns to such small tolerances, however, is very difficult when the distance between the, emission source and the surface of the wafer varies because the surface of the wafer is not uniformly planar. In fact, when the surface of the wafer is not uniformly planar, several devices on the wafer may be defective. Thus, CMP processes must create a highly uniform, planar surface.
FIG. 2
illustrates a specific application of the CMP process in which a wafer
50
is polished on polishing pad
40
. The wafer
50
has a substrate
60
, a number of device features
62
formed on the substrate
60
, a large area feature
80
positioned on the substrate
60
, and a dielectric layer
70
deposited over the substrate
60
. A large cavity
72
in the dielectric layer
70
is formed around the large area feature
80
, and a number of vias
74
are positioned over the device features
62
. A first layer of conductive material
90
is deposited over the dielectric layer
70
and the large area feature
80
to fill the vias
74
. The first layer of conductive material
90
is subsequently polished with a CMP process to electrically isolate the conductive material in the vias
74
from each other so as to create interconnects
92
between the device features
62
and the top surface
71
of the dielectric layer
70
. After the first conductive layer
90
is polished, a second conductive layer (not shown) is deposited over the wafer and patterned (not shown) on the top surface
71
of the dielectric layer
70
to form conductive lines. The first conductive layer
90
is typically tungsten (W), and the second conductive layer is typically aluminum (Al). The aluminum layer, and generally the tungsten layer as well, are opaque layers of material. The large area feature
80
is typically an alignment array with a number of lines
82
that a stepper machine (not shown) scans to align photo-patterns and other fabrication processes on the surface of the wafer
50
, such as when the aluminum layer is patterned to form conductive lines. Thus, because aluminum is opaque and the topography of the array of lines
82
must be visible to the stepper machine, it is necessary to etch the cavity
72
in the dielectric layer
70
so that the stepper machine can scan the contour of the tungsten on the lines
82
.
One problem with polishing the wafer
50
with a CMP process is that the resulting surface is not uniformly planar because the polishing pad
40
penetrates into the large opening
72
beyond the top surface
71
of the dielectric layer
70
. During the polishing process, the polishing surface
42
of the polishing pad
40
conforms to the surface of the conductive layer
90
and often penetrates into the cavity
72
over the large area feature
80
. The penetration of the polishing surface
42
shown in
FIG. 2
is exaggerated to emphasize the effect over large area features. The polishing pad
40
thus causes the surface of the wafer to “dish” at the surfaces
94
adjacent to the cavity
72
. In extreme cases, the polishing pad may even contact the conductive layer
90
over the array of lines
82
. As a result, the finished surface of the wafer
50
is not uniformly planar and the topography of the tungsten on top of the lines
82
may be substantially altered. The topography of the resulting aluminum layer on top of the tungsten over the lines
82
may also be altered such that a stepper cannot properly align the pattern on the aluminum layer.
In light of the problems with CMP processing of conventional wafers with large area features, it would be desirable to develop a device and method that reduces dishing caused by chemical-mechanical polishing over large area features.
SUMMARY OF THE INVENTION
The inventive semiconductor wafer reduces dishing over large area features in chemical-mechanical polishing processes. The semiconductor wafer has a substrate with an upper surface, a large area feature formed on the substrate, and a separation layer deposited on the substrate. The separation layer has a top surface and a cavity extending from the top surface towards the upper surface of the substrate. The large area feature is positioned in the cavity of the separation layer, and a support structure is positioned in the cavity. In one embodiment, the support structure is a pillar with a base positioned between components of the large area feature and a crown positioned proximate to a plane defined by the top surface of the separation layer. In operation, the support structure substantially prevents the polishing pad of a polishing machine from penetrating into the cavity beyond the top surface of the separation layer.
In an inventive method for fabricating a semiconductor wafer, a large area feature is formed on an upper surface of a substrate. A separation layer is deposited over the substrate and the large area feature, and then a cavity is etched in the separation layer above the large area feature. A pillar is formed in the cavity, and an upper layer of material is subsequently deposited over the wafer.

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