Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Ball or nail head type contact – lead – or bond
Reexamination Certificate
2001-12-28
2003-12-02
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Ball or nail head type contact, lead, or bond
C257S347000, C257S737000, C257S738000, C257S778000
Reexamination Certificate
active
06657312
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a structure of a flip chip using an SOI (Silicon On Insulator) substrate and a method of manufacturing the same.
2. Description of the Background Art
FIGS. 25 through 28
are schematic views for explaining a soldering method using a flip chip.
FIGS. 25 and 26
are top views and
FIGS. 27 and 28
are sectional views. Referring to
FIG. 25
, a plurality of electrode pads
103
made of aluminum are formed on an upper surface of a flip chip
100
already undergone dicing. A silicon nitride film
104
is formed on a part of the upper surface of the flip chip
100
where the electrode pads
103
are not formed. Referring to
FIG. 26
, a bump
105
is formed on the electrode pads
103
of the flip chip
100
. Referring to
FIG. 27
, the flip chip
100
on which the bump
105
is formed is turned upside-down, and thereafter, is mounted on a pattern formed on a wiring substrate
170
by soldering. Further, as shown in
FIG. 28
, there is a case where the flip chip
100
is mounted on the wiring substrate
170
, and thereafter, is sealed with resin
171
.
FIG. 29
is a sectional view showing a structure of a conventional flip chip using an SOI substrate. A layer
102
is formed on a silicon substrate
101
. The layer
102
includes a BOX (Burried Oxide) layer and a silicon layer of the SOI substrate, a semiconductor element selectively formed on the silicon layer and an interlayer insulation film formed on the semiconductor element and the silicon layer. A plurality of electrode pads
103
a
to
103
d
are formed on the layer
102
. The electrode pads
103
a
to
103
c
are electrically connected to the semiconductor element through a tungsten plug filling a contact hole formed in the interlayer insulation film and a wiring made of aluminum. The electrode pad
103
d
is electrically connected to the silicon substrate
101
through a conductive plug
173
made of polysilicon, tungsten or the like, which fills a contact hole
172
extending from an upper surface of the layer
102
to reach an upper surface of the silicon substrate
101
. Further formed on the layer
102
is a silicon nitride film
104
patterned so as to expose the electrode pads
103
a
to
103
d
. Formed on the electrode pads
103
a
to
103
d
are bumps
105
a
to
105
d
made of solder, respectively. The bump
105
d
is provided for fixing a potential of the silicon substrate
101
.
FIGS. 30 through 34
are sectional views showing manufacturing steps of the conventional flip chip shown in
FIG. 29
in sequential order. Referring to
FIG. 30
, an SOI wafer is prepared first, and after carrying out usual processes of manufacturing a semiconductor, a structure is obtained in which the layer
102
is formed on the silicon substrate
101
. Next, referring to
FIG. 31
, a photoresist
174
having a predetermined opening pattern is formed on the layer
102
by photolithography. Next, the layer
102
is subjected to anisotropic dry etching using the photoresist
174
as an etching mask so as to expose a part of the upper surface of the silicon substrate
101
. Thereby formed is the contact hole
172
having its side surface defined by the layer
102
and its bottom surface defined by the upper surface of the silicon substrate
101
. Such a step requires anisotropic dry etching with a very high aspect ratio.
Next, referring to
FIG. 32
, after removing the photoresist
174
, a conductive film
175
made of a polysilicon film, a tungsten film or the like is formed on an entire surface by CVD method in a thickness that can fill the contact hole
172
. Next, Referring to
FIG. 33
, the polysilicon film
175
is removed by CMP method until an upper surface of the layer
102
is exposed. Thereby, the contact hole
172
is filled with the polysilicon
173
. Next, referring to
FIG. 34
, after forming an aluminum film on the layer
102
, the aluminum film is patterned, thereby forming the electrode pads
103
a
to
103
d
at predetermined positions on the layer
102
. The electrode pad
103
d
is in contact with the polysilicon
173
.
Subsequently, after forming a silicon nitride film on the entire surface, the silicon nitride film is patterned, thereby forming the silicon nitride film
104
. Next, after dicing the SOI wafer, the bumps
105
a
to
105
d
are formed on the electrode pads
103
a
to
103
d
, respectively, thereby obtaining the structure shown in FIG.
29
.
In such a conventional flip chip, however, the electrode pad
103
d
is electrically connected to the silicon substrate
101
through the polysilicon
173
which fills the contact hole
172
formed in the layer
102
. Accordingly, this requires the steps of: forming the contact hole
172
in the layer
102
by anisotropic dry etching with a very high aspect ratio (FIG.
31
); forming the polysilicon film
175
on the entire surface (FIG.
32
); and etching back the polysilicon film
175
by CMP method (FIG.
33
), resulting in difficulties in the manufacturing steps.
SUMMARY OF THE INVENTION
A first aspect of the present invention is directed to a semiconductor device. The semiconductor device comprises: an SOI substrate including a semiconductor substrate, an insulation layer formed on a main surface of the semiconductor substrate and a semiconductor layer formed on the insulation layer; a semiconductor element selectively formed on the semiconductor layer; an interlayer insulation film formed on the semiconductor element and the semiconductor layer; a first electrode pad formed on a main surface of the interlayer insulation film, being electrically connected to the semiconductor element; a first bump formed on the first electrode pad; a hollow selectively formed extending from the main surface of the interlayer insulation film to reach the main surface of the semiconductor substrate; and a second bump formed on the semiconductor substrate which defines a bottom surface of the hollow.
According to a second aspect of the present invention, the semiconductor device of the first aspect further comprises a second electrode pad formed on the main surface of the semiconductor substrate which defines the bottom surface of the hollow, wherein the second bump is formed on the second electrode pad.
According to a third aspect of the present invention, the semiconductor device of the second aspect further comprises an impurity region formed in the main surface of the semiconductor substrate which defines the bottom surface of the hollow.
A fourth aspect of the present invention is directed to a method of manufacturing a semiconductor device. The method comprises the steps of: (a) preparing an SOI substrate including a semiconductor substrate, an insulation layer formed on a main surface of the semiconductor substrate and a semiconductor layer formed on the insulation layer; (b) selectively forming a semiconductor element on the semiconductor layer; (c) forming an interlayer insulation film on the semiconductor element and the semiconductor layer; (d) forming a first electrode pad on a main surface of the interlayer insulation film, the first electrode pad being electrically connected to the semiconductor element; (e) selectively forming a hollow which extends from the main surface of the interlayer insulation film to reach the main surface of the semiconductor substrate; and (f) forming a first bump on the first electrode pad and a second bump on the semiconductor substrate which defines a bottom surface of the hollow, respectively.
According to a fifth aspect of the present invention, the method of the fourth aspect further comprises the step of (g) forming a second electrode pad on the main surface of the semiconductor substrate which defines the bottom surface of the hollow, the step (g) being executed after the step (e) and before the step (f), wherein the second bump is formed on the second electrode pad in the step (f).
According to a sixth aspect of the present invention, in the method of the fif
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Soward Ida M.
Zarabian Amir
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