Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2002-07-12

2003-12-09

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230080, C365S230030

Reexamination Certificate

active

06661734

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-212590, filed Jul. 12, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device with a word drive line reset circuit of a type in which a potential of the word drive line through which a word line drive voltage is supplied is reset in two stages, and it is used, for example, in a DRAM (dynamic random access memory) employing NWR (negative word line reset) system.
2. Description of the Related Art
In a DRAM, it is preferred to decrease the current consumption by maintaining the cut-off current (Ioff) of a memory cell transistor at low level, and also to cope with the trend of higher operating speed and lower supply voltage by lowering the threshold voltage of a memory cell transistor.
To satisfy such contradictory demands, hitherto, the gate oxide film of the memory cell transistor has been improved to have a high breakdown voltage and the gate film thickness has been thinned, and using the improved S-factor of the memory cell transistor, a low threshold voltage was maintained while keeping the Ioff at low level.
However, as the DRAM becomes finer and the supply voltage is further lowered, it is becoming hard to satisfy the contradictory requirements of low level of Ioff and low threshold voltage of the memory cell transistor. For example, since the electric field (Eox) applied to the gate oxide film is 6 MV/cm or more at the present, the conventional technique is beyond the limit.
To solve this problem, the NWR system has been proposed. In the NWR system, the resetting potential of the word line is set at a negative potential (Vnn), the gate-source voltage Vgs when the memory cell transistor is off is set at a negative value (Vgs<0), and therefore both low Ioff level and low threshold voltage are realized.
Here is discussed the amount Q of electric charge flowing into a power supply line Vnn in the resetting operation of the word line. The electric charge amount Q, as expressed in formula Q=CV, is expressed by the product of capacity C and potential difference V.
First considering the capacity, the word lines are connected to gate electrodes of a plurality of memory cells, and have the coupling capacity with bit lines and memory cell capacitors, and hence the capacity is large. Word drive lines are shared by a plurality of row decoders, and hence the capacity is also relatively large.
As for the potential difference, a boosting potential (Vpp) is generally used as the setting potential of the word lines in order to write “H” level data in the memory cell. Accordingly, since the electric charge amount Q is expressed by the product of capacity C and potential difference V as described above, then when resetting the word line, the voltage swing Vpp-Vnn is large. Therefore, in resetting operation of the word line, the amount of electric charge flowing into the power supply line Vnn is very large. As a result, a large current flows into the power supply line Vnn in a relatively short time.
Vnn is generally produced in a chip by means of a charge pump circuit, and supplied to the necessary circuits in the chip via the power supply line Vnn composed of metal wiring or the like. The charge pump circuit is generally high in output impedance. Thus, when a large current flows into the power supply line Vnn in a relatively short time, the potential of the power supply line Vnn locally rises, which is known as a power supply bounce.
Since the word line in an inactivated state is electrically connected to a Vnn power supply line, the potential of the inactivated word line is boosted by this power supply bounce, and the electric charge accumulated in the memory cell may leak.
To suppress the power supply bounce, it may be attempted to provide a plenty of stabilizing capacitors for Vnn near the row decoders, or decrease the RC product of the power supply line wiring (decrease the resistance of wiring material, decrease the dielectric constant of insulating material, or increase the width of power supply wiring).
In the former case, however, the problem is the increase of chip area, and hence it is not realistic to provide stabilizing capacitors for Vnn in the core circuit. In the latter case, improvement or modification of wiring material and insulation film material may lead to increase in the cost of development, increase in the period of development, and increase in the necessary chip area. Also in the latter case, if low RC product of wiring material is realized, a large capacity is needed in the charge pump circuit for generating Vnn, rendering the necessary chip area large.
To suppress the power supply bounce of the power supply line of such negative potential (Vnn) and to reduce the load to the negative potential generating circuit, for example, as disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2000-36191, a method of resetting by dividing the word line potential of DRAM in two stages is proposed (known as t within wo-stage resetting method). In this two-stage resetting method, when resetting the word lines, the potential of the word lines and the word drive lines is first set at the grounding potential (Vss), and then set at Vnn, so that an electric current flown into the Vnn power supply line may be decreased than conventional.
FIG. 5A
is a block diagram of an example of connectional relation between a word drive line drive circuit and a plurality of row decoders in a conventional DRAM with the two stage reset system. In
FIG. 5A
, the word drive line drive circuit resets the word drive line potential in two stages, and thus resets the word line potential in two stages.
In
FIG. 5A
, a word drive line drive circuit (WDRV DRV)
41
is provided in each unit block of a memory cell array, that is, in every sub array (not shown). A block select signal BlockSel for selecting the sub array and a row address signal Addr for specifying a selection line within the sub array are inputted to the word drive line drive circuit (WDRV DRV)
41
. Also, a first reset control signal Reset<
0
> and a second reset control signal Reset<
1
> are inputted to the word drive line drive circuit (WDRV DRV)
41
.
A plurality of sub row decoders (SRD#
0
, SRD#
1
, . . . , SRD#n)
420
to
420
n
are provided corresponding to a plurality of sub word lines SWL<
0
>, SWL<
1
), . . . , SWL<n> in every sub array. A word drive voltage is supplied from the word drive line drive circuit
41
through first word drive line wdrv_p to the sub row decoders (SRD#
0
, SRD#
1
, . . . , SRD∩n)
420
to
420
n
, and a word drive signal is supplied from the word drive line drive circuit
41
through second word drive line wdrv_n to the sub row decoders (SRD#
0
, SRD#
1
, . . . , SRD#n)
420
to
420
n
. Also, the sub row decoders (SRD#
0
, SRD#
1
, . . . , SRD#n)
420
to
420
n
receive and decode an address signal MWL for specifying a selection sub word line (a row address input other than the row address signal Addr for specifying the selection line within the sub array) to selectively drive a corresponding sub word line SWL<
0
>, SWL<
1
>, . . . , SWL<n>.
A delay circuit (Delay)
43
receives the first reset control signal Reset<
0
>, and produces the second reset control signal Reset<
1
>.
FIG. 5B
is a signal chart showing the timing relation between the reset control signal Reset<
0
> and the reset control signal Reset<
1
> in the block diagram in FIG.
5
A.
FIG. 6
is a circuit diagram of the word drive line drive circuit
41
in FIG.
5
A.
In
FIG. 6
, reference numeral
51
is a decoding circuit,
52
is a dynamic latch circuit,
53
is a level shifting circuit,
54
is a first word drive line drive circuit, and
55
is a second word drive line drive

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