Sticky bit value predicting circuit

Details Sticky bit value predicting circuit Sticky bit value predicting circuit

1999-12-21

2003-02-04

Malzahn, David H. (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

06516333

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a sticky bit value predicting circuit for use in a multiplication circuit.
2. Description of the Related Art
FIG. 9
shows a prior art mantissa multiplication circuit.
A product of a multiplicand X and a multiplier Y is calculated in a multiplier
10
, the circuit is provided with, for example, a Wallace tree and a Booth recorder for a high speed processing. The multiplicand X and the multiplier Y each have ‘1’ as a value of the most significant bit (MSB) and are normalized so as to respectively be 1≦X<2 and 1≦Y<2. The product Z is rounded in a rounding circuit
11
and a product ZH′ is obtained.
FIG. 10
is an illustration a sticky bit used in a rounding operation in a case where a multiplicand and a multiplier each are 8 bits and the product is 16 bits.
Since 1≦Z<4, the integral part of the product Z having bits Z
15
to Z
0
is comprised of higher-order two bits Z
15
and Z
14
, wherein Z
15
=‘1’ or Z
14
=‘1.’
Denoting higher-order 8 bits of the product Z as ZH normalized as MSB=‘1’ before rounding, in a case where Z
15
=‘0’ and Z
14
=‘1’, ZH is expressed as Z
14
to Z
7
, and therefor the least significant bit (LSB) is Z
7
and a round bit R is Z
6
. The sticky bit S is “1” when any one of Z
5
to Z
0
bits is ‘1,’ or else the sticky bit S is “0.” A rounding operation on the product ZH is performed using the round bit R and the sticky bit S according to the IEEE (The Institute of Electrical and Electronic Engineers, Inc.) Binary Floating-Point Standard
754
, and the result is Z′=ZH or Z′=ZH+1.
In a case where Z
15
=‘1,’ the product Z is right-shifted by one bit to normalize. Using Z
15
to Z
0
before this shifting, the LSB of the product ZH is Z
8
and the round bit is Z
7
. The OR of Z
7
and the provisional sticky bit S obtained before the shift is performed to obtain an actual sticky bit S.
If the sticky bit S is obtained with OR gates
12
to
16
after the product Z is obtained, it takes a long time to obtain a rounded product ZH′.
Considering such circumstances, U.S. Pat. No. 4,928,259 has provided a sticky bit value predicting circuit
20
shown in
FIG. 9
, whereby the sticky bit S is obtained in parallel with a multiplication operation.
Referring back to
FIG. 10
, the number M of trailing Os is equal to the sum of the number C of trailing 0s of the multiplicand X and the number D of trailing 0s of the multiplier Y. For example as shown in
FIG. 10
, in a case where C=2 and D=3, then M=5. In a case where M≧6, then S=‘0,’ and in a case where M<6, then S=‘1.’
Referring back to
FIG. 9
, in the sticky bit value predicting circuit
20
, the numbers C and D of trailing 0s of the multiplicand X and the multiplier Y are obtained in priority encoders (trailing zero encoders)
21
and
22
, respectively, the sum M of the numbers C and D of the trailing 0s are calculated in an adder
23
, and M is compared with a predetermined value CONST in a comparator
24
, thereby obtaining the sticky bit S as a result.
However, circuit scales of the priority encoders
21
and
22
are comparatively large. As described in U.S. Pat. No. 4,928,259, a priority encoder of 5 bits comprises thirteen encoders
21
of 4 bits provided at a first stage, three encoders
21
of 4 bits and three multiplexers with
4
inputs provided at a second stage, and one encoder
21
of 4 bits and one multiplexer with 4 inputs provided at a third stage.
SUMMARY OF THE INVENTION
Accordingly, it is an object according to the present invention to provide a sticky bit value predicting circuit with a simpler configuration and a semiconductor device provided with the same.
In the present invention, there is provided a sticky bit value predicting circuit for predicting a sticky bit value of a product of a first mantissa and a second mantissa, comprising: a bit pattern generation circuit for generating a bit pattern of sticky bit values for any number of trailing 0s of the second mantissa on the basis of a trailing zero bit pattern of the first mantissa; a priority encoder for providing a selection control value, corresponding to a bit position of ‘1’ whose priority is higher with lower order bit side, in response to the second mantissa; and a sticky bit selection circuit for selecting one bit from the generated bit pattern as a sticky bit value depending on the selection control value.
With the present invention, since a bit pattern generation circuit and a sticky bit selection circuit each with a simpler configuration are employed instead of a prior art configuration including priority encoders, an adder and a comparator, a configuration of the sticky bit value predicting circuit becomes simpler as a whole, which in turn makes the circuit scale smaller than a prior art one.
Other aspects, objects, and the advantages of the present invention will become apparent from the following detailed description taken in connection with the accompanying drawings.


REFERENCES:
patent: 4928259 (1990-05-01), Galbi et al.
patent: H1222 (1993-08-01), Brown et al.
patent: 5260889 (1993-11-01), Palaniswami
patent: 5341319 (1994-08-01), Madden et al.
patent: 5867722 (1999-02-01), Whitted et al.
patent: 5944773 (1999-08-01), Chao et al.
patent: 6044391 (2000-03-01), Chao et al.
patent: 0 655 675 (1995-05-01), None

Affiliated with

Also associated with

Rating

Sticky bit value predicting circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Sticky bit value predicting circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Sticky bit value predicting circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3166944