Power-on reset circuit with well-defined reassertion voltage

Details Power-on reset circuit with well-defined reassertion voltage Power-on reset circuit with well-defined reassertion voltage

1996-10-04

1998-10-13

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327198, H03K 1722

Patent

active

058217878

ABSTRACT:
A power-on reset (POR) circuit (200) asserts a POR signal when the supply voltage (V.sub.CC) is turned on. As the supply voltage increases, the POR signal is deasserted when the supply voltage reaches a voltage (V.sub.POR1) sufficiently high to make storage elements in a controlled circuit fully operational. The POR signal is kept deasserted until the power supply voltage level drops to a level low enough (V.sub.POR2) to render the storage elements in the controlled circuit incapable of holding accurate data. The V.sub.POR2 level that triggers the reassertion of the POR signal is lower than the V.sub.POR1. Additional circuitry insures that the POR signal is reasserted when V.sub.CC drops to the V.sub.POR2 level by sampling the transistor threshold voltages of the circuit. Another control signal allows the POR signal to be forcibly generated.

REFERENCES:
patent: 5151614 (1992-09-01), Yamazaki et al.
patent: 5243233 (1993-09-01), Cliff
patent: 5319255 (1994-06-01), Garverick et al.
patent: 5498987 (1996-03-01), Nelson
patent: 5517144 (1996-05-01), Nakashima
patent: 5534804 (1996-07-01), Woo
patent: 5612642 (1997-03-01), McClintock

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