Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2002-04-29
2003-11-11
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
C438S009000, C438S015000, C438S016000, C438S017000, C438S012000
Reexamination Certificate
active
06645781
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to the field of electronic device processing and more particularly to a method to determine a complete etch in integrated devices.
BACKGROUND OF THE INVENTION
The use of vias and interconnects within a complex integrated electronic device is well known. Where interconnection is maintained, current may pass through the via from one semiconductor component to another within the integrated electronic device. During the formation of a via, an etch may be performed to form a cavity in a dielectric layer that separates semiconductor components. Additionally, a series of etches may be performed and each may be selective to a particular material or layer within the integrated device.
The ability to create complex integrated electronic devices at reasonable cost is directly related to the ability to determine accurately and quickly whether an etch is complete. Former techniques for determining complete etch include using physical failure analysis to determine the depth of the etch from a cross-sectional profile, or using an in-line probe to determine the electrical performance. Physical failure analysis is destructive to the wafer or the integrated device. Additionally, physical failure analysis is difficult and time consuming. The in-line probe is also time consuming as it may take several weeks to receive electrical results after an etch is performed. Neither technique allows for detection of incomplete etch defects during in-line production. Therefore, it is desirable to provide for immediate detection of an incomplete etch within integrated devices.
SUMMARY OF THE INVENTION
From the foregoing, it may be appreciated by those skilled in the art that a need has arisen to immediately determine whether a complete etch was made in an integrated device. In accordance with the present invention, a method for determining a complete etch in integrated devices is provided that substantially eliminates or greatly reduces at least some of the disadvantages and problems associated with previous semiconductor fabrication techniques and systems.
According to a particular embodiment of the present invention, a method for determining a complete etch in integrated devices is disclosed which includes performing an etch in an intermediate layer to form a via. The via is inspected using a scanning electron microscopy. The scanning electron microscopy detects a level of brightness associated with the via in relation to a background shade. Whether the etch reached an etch-stop layer is determined by comparing the level of brightness associated with the via to the background shade.
The present invention provides various technical advantages over conventional semiconductor fabrication techniques. In particular embodiments, a technical advantage may be that an incomplete etch may be detected more easily. Another technical advantage may be detection of an incomplete etch in an isolated Kelvin via. Further, process engineers may be able to detect an incomplete etch immediately during in-line production. Another technical advantage may be that whole lots of semiconductor wafers do not have to be set aside while a sample is examined by physical failure analysis, such as transmission electron microscopy (TEM). Consequently, process engineers may be able to fix the problem before subsequent defective lots are produced.
Another technical advantage may be that the method is not destructive to the wafer. Once a wafer is inspected with a complete etch, it may be returned to the lot and processing continued. Another technical advantage of particular embodiments may be that the method may be performed by automated tool setup so that engineers and technicians may better allocate their time and resources.
Embodiments of the present invention may have some, all, or none of the following technical advantages. Other technical advantages of the present invention may be readily apparent to one skilled in the art from the figures, description, and claims included herein.
REFERENCES:
patent: 5148461 (1992-09-01), Shoulders
patent: 5171992 (1992-12-01), Clabes et al.
patent: 5585211 (1996-12-01), Firstein et al.
patent: 5616926 (1997-04-01), Shinada et al.
patent: 5991699 (1999-11-01), Kulkarni et al.
patent: 6046796 (2000-04-01), Markle et al.
patent: 6180497 (2001-01-01), Sato et al.
patent: 6250143 (2001-06-01), Bindell et al.
patent: 6288417 (2001-09-01), Nickel et al.
patent: 6365423 (2002-04-01), Heinlein et al.
patent: 6433561 (2002-08-01), Satya et al.
patent: 6445199 (2002-09-01), Satya et al.
patent: 6509197 (2003-01-01), Satya et al.
Jiang Ping
Park Heung-soo
Brady III W. James
Garner Jacqueline J.
Luk Olivia
Niebling John F.
Telecky , Jr. Frederick J.
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