Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2001-05-21
2003-12-23
Eckert, George (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S536000, C257S537000, C257S540000, C257S541000
Reexamination Certificate
active
06667538
ABSTRACT:
RELATED APPLICATION DATA
The present application claims priority to Japanese Application No. P2000-153445 filed May 24, 2000 which application is incorporated herein by reference to the extent permitted by law.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a semiconductor resistance element and a fabrication method thereof.
A semiconductor resistance element configured as a semiconductor region formed by doping an impurity in the surface of a semiconductor substrate is one of elements widely used as components of a semiconductor integrated circuit.
A known resistance element is typically formed by doping an n-type impurity in a semi-insulating compound semiconductor substrate, for example, a semi-insulating GaAs substrate at a low impurity concentration. The structure of such a resistance element and a fabrication method thereof will be described below with reference to process diagrams shown in
FIGS. 3A
to
3
D and
FIGS. 4A
to
4
D.
As shown in
FIG. 3A
, a protective film
2
made from SiN and having a thickness of 50 nm is formed overall on a semi-insulating semiconductor substrate
1
by a plasma CVD (Chemical Vapor Deposition) process. A photoresist layer
3
is once formed overall on the SiN protective film
2
, and a portion, positioned over a semiconductor resistance element forming area, of the photoresist layer
3
is removed by photolithography, to form an opening
3
w.
Ions of Si representative of an n-type impurity are implanted in the surface of the semi-insulating semiconductor substrate
1
through the opening
3
W formed in the protective film
2
, to form an impurity doped region
4
.
As shown in
FIG. 3B
, the photoresist layer
3
is removed, and a photoresist layer
5
is once formed overall on the protective film
2
, and portions, positioned over electrode extraction region forming areas at both ends of the semiconductor resistance element forming area, of the photoresist layer
5
are removed by photolithography, to form two openings
5
w.
Ions of Si as the n-type impurity are implanted in the surface of the semi-insulating semiconductor substrate
1
at a high concentration through the openings
5
w,
to form two high concentration impurity doped regions
6
.
As shown in
FIG. 3C
, the photoresist layer
5
and the surface protective layer
2
are removed, and then the semi-insulating semiconductor substrate
1
is annealed in an arsine atmosphere, to activate ions of Si in the impurity doped regions
4
and
6
. As a result, a semiconductor resistance region
4
R having a specific resistivity is formed from the region
4
, and electrode extraction regions
6
R each having a specific low resistivity are formed from the regions
6
.
As shown in
FIG. 3D
, an insulating layer
7
made from SiN and having a thickness of 300 nm is once formed, by the plasma CVD process, overall on the surface of the semi-insulating semiconductor substrate
1
in which the regions
4
R and
6
R have been formed. A photoresist layer
8
is formed on the insulating layer
7
, and two openings
8
w
are formed in the photoresist layer
8
at positions over the electrode extraction regions
6
R. Portions, positioned over the electrode extraction regions
6
R, of the insulating layer
7
are removed by reactive ion etching through the openings
8
w
, to form two electrode contact windows
7
w.
As shown in
FIG. 4A
, an electrode metal layer
9
is formed overall on the photoresist layer
8
in such a manner as to be in contact with the electrode extraction regions
6
R exposed to the outside through the contact windows
7
w
. The electrode metal layer
9
is formed by sequentially forming an AuGe layer having a thickness of 150 nm and a Ni layer having a thickness of 50 nm by a vapor-deposition process.
As shown in
FIG. 4B
, the portion, on the photoresist layer
8
, of the metal layer
9
is selectively removed by a lift-off process, that is, by removing the photoresist layer
8
, whereby only portions, on the electrode extraction regions
6
R, of the metal layer
9
remain. The substrate
1
is then heated in a forming gas at about 450° C., to form a pair of electrodes
9
R by the metal layer
9
being in ohmic contact with the electrode extraction regions
6
R.
As shown in
FIG. 4C
, a wiring metal layer
10
for forming wiring is formed overall on the insulating layer
7
. The wiring metal layer
10
is formed by sequentially forming a Ti layer having a thickness of 50 nm, a Pt layer having a thickness of 50 nm, and an Au layer having a thickness of 200 nm by the vapor-deposition process. A photoresist layer
11
is formed on the wiring metal layer
10
, and is patterned by photolithography in such a manner as to remove portions, other than wiring forming areas, of the photoresist layer
11
while leaving the wiring forming areas of the photoresist layer
11
.
As shown in
FIG. 4D
, the wiring metal layer
10
is etched by an ion-milling process using the patterned photoresist layer
11
as a mask, to form wiring portions
10
R being in ohmic-contact with the electrodes
9
R.
In this way, a semiconductor device having a semiconductor resistance element
12
is formed. With this structure of the semiconductor device, the resistance of the semiconductor resistance element
12
can be set to a desired value by suitably selecting an accelerating voltage applied to Si atoms and the dose of the Si atoms in ion implantation of Si for forming the semiconductor resistance region
4
R.
Such a resistance element can be fabricated at a low cost; however, it has a problem that if the impurity concentration in the semiconductor resistance region
4
R is reduced for ensuring a high sheet resistance of the region
4
R, an electric resistance of the region
4
R largely varies depending on a substrate potential.
The reason for this is due to one form of a so-called back gate effect.
FIG. 6
is a graph showing one example of measuring the back gate effect exerted on a current-voltage characteristic of a semiconductor resistance element configured as a n-type semiconductor resistance region
4
R formed in a semi-insulating semiconductor substrate
1
shown in FIG.
5
. In this example, measurement is performed by changing a substrate potential V
sub
in a range of −6V to 0 V.
The substrate potential is, as shown in
FIG. 5
, applied from a substrate electrode
13
provided at a position apart from the semiconductor resistance region
4
R formed in the substrate
1
.
As is apparent from the data shown in
FIG. 6
, as the substrate potential V
sub
becomes smaller on the negative side, an electrical resistance of the semiconductor resistance region
4
R becomes larger and thereby a saturated current flowing in the semiconductor resistance region
4
R becomes smaller. The reasons for this may be considered to be due to the fact that a spatial charge layer between the semiconductor resistance region
4
R and the semi-insulating substrate region of the substrate
1
is spread to the semiconductor resistance region
4
R side by the substrate potential V
sub
to reduce a sheet carrier concentration in the semiconductor resistance region
4
R.
Even when such a back gate effect emerges, if the strength of the back gate effect is stabilized, the circuit can be designed in consideration of the back gate effect.
In the real process, however, the strength of the back gate effect may be often unstable. The reason for this may be considered to be due to the fact that an effective acceptor concentration around the resistance layer varies depending on factors associated with the substrate or process (see N. Goto, et al., “Two Dimensional Numerical Simulation of Side-Gating Effect in GaAs MESFET's”, IEEE ED-17, No. 8, 1990).
Accordingly, to fabricate circuits using such resistance elements at a high yield, the above-described effective acceptor concentration must be controlled to be usually kept constant.
However, since the derivation of such an acceptor is not necessarily clear, it is not easy to control the acceptor concentration.
SUMMARY OF THE
Eckert George
Sonnenschein Nath & Rosenthal LLP
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