Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2003-01-07
2003-12-23
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185110, C365S230030
Reexamination Certificate
active
06667905
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit technique and, further, to a command control method for use in a semiconductor integrated circuit having therein a plurality of memory circuits. The invention relates to a technique which is effective for use in, for example, enabling repair of a defective bit and in the adjustment of the operation timing of a circuit after a chip is mounted.
Hitherto, in a semiconductor integrated circuit having therein a semiconductor memory, such as a RAM (Random Access Memory) or a memory circuit, in order to improve the yield by repairing a defective bit (defective memory cell) included in a memory array, a redundancy circuit, such as an address setting circuit for storing a spare memory column, a spare memory row and a defect address, is provided. A defect address in such a redundancy circuit is generally set by using a programmable fuse activated by a laser or the like.
In a repairing method involving the steps of blowing a fuse using a laser to store defect address information, comparing an input address with the stored defect address information, and replacing a defective memory row or a defective memory column with a spare memory row or a spare memory column, a fuse has to be blown before the memory chip is sealed in a package. A defect occurring after the memory chip is sealed in the package cannot be repaired, and this causes a problem in that a sufficiently improved yield cannot be achieved.
A technique in which a nonvolatile memory, such as an EEPROM (Electrically Erasable Programmable Read Only Memory), is provided in a chip of a DRAM (Dynamic Random Access Memory) for storing defect address information, has been proposed. According to such a technique, even after a chip is sealed in a package, defect address information can be written into the EEPROM. Consequently, a defect occurring after the chip is sealed in the package can be repaired, so that the yield can be improved.
It was, however, clarified by examination of the inventor of the present invention that the conventionally proposed repairing method using an EEPROM has the following problems. Although defect address information can be written in the EEPROM even after the chip is sealed in the package, in a state where the chip is mounted on a printed wiring board (hereinbelow, called a board), a module, or the like, the defect address information cannot be written. A new control terminal for writing information to the EEPROM and a source terminal for applying a high voltage necessary for writing/erasing information to/from the EEPROM are necessary, and so compatibility with a conventional memory cannot be maintained. The memory repairing method is disclosed in Japanese Unexamined Patent Application Laid-Open No. Hei 8(1996)-31196 and Japanese Patent Application No. Hei 11(1999)-23631 (corresponding to U.S. application Ser. No. 09/493,280).
SUMMARY OF THE INVENTION
An object of the invention is to provide a semiconductor integrated circuit having therein a memory circuit, such as a RAM, in which defect address information can be easily written even in a state where a chip is sealed in a package and is further mounted on a board, module, or the like, thereby making it possible to repair a defective bit in the memory circuit and accordingly achieve an improved yield.
Another object of the invention is to provide a semiconductor integrated circuit having therein a memory circuit such as a RAM, in which the operation timing of the circuit is adjusted to increase the operation margin, thereby enabling the circuit to operate at higher speed.
Still another object of the invention is to provide a semiconductor integrated circuit in which a chip can be prevented from losing compatibility with a conventional chip due to an increase in the number of terminals or a different pin arrangement.
The foregoing objects of the invention, other objects, and novel features will become apparent from the description of the specification and the attached drawings.
The outline of representative aspects and features of the invention disclosed in this application will be described as follows.
In a semiconductor integrated circuit comprising: a first storage (
11
) having a memory cell of a first configuration; a second storage (
20
) having a memory cell of a second configuration; a plurality of control terminals for receiving a plurality of control signals from the outside; and a plurality of address terminals for receiving a plurality of address signals for selecting a memory cell in the first storage, an operation of the first storage is instructed according to a first combination (CS, RAS, CAS, and WE=“L”, and A
7
=“O”) of the signals (CS, RAS, CAS, and WE) supplied to the control terminals and at least a part (A
7
) of the signals supplied to the address terminals, and an operation of the second storage is instructed according to a second combination (CS, RAS, CAS, and WE=“L”, and A
7
=“1”) of the signals supplied to the control terminals and at least a part of the signals supplied to the address terminals.
According to the above, the first and second storages having memory cells of different configurations can be accessed by the same command. Consequently, the first and second storages can be separately operated without providing a new external control terminal.
Desirably, the signals supplied to the control terminals in the first combination and those in the second combination are the same, and a signal supplied to the address terminal in the first combination and that in the second combination are different from each other. Consequently, by the signal supplied to the address terminal, the instruction to the first storage and the instruction to the second storage by the same command can be discriminated from each other. Thus, the first and second storages can be operated separately without providing a new external terminal.
In a semiconductor integrated circuit comprising: a first storage having a memory cell of a first configuration; a second storage having a memory cell of a second configuration; a plurality of control terminals for receiving a plurality of control signals from the outside; and a plurality of address terminals for receiving a plurality of address signals for selecting a memory cell in the first storage, a command for instructing an operation of the first storage, which is specified by a combination of the control signals supplied to the control terminals after the operation of the first storage or the operation of the second storage is instructed and a command for instructing the operation of the second storage are the same code. With this configuration, while effectively using the combinations of a relatively small number of control signals, the first and second storages can be operated separately.
Further, in a semiconductor integrated circuit comprising: a first storage having a memory cell of a first configuration; a second storage having a memory cell of a second configuration; a plurality of control terminals for receiving a plurality of control signals from the outside; and a plurality of address terminals for receiving a plurality of address signals for selecting a memory cell in the first storage, an operation of the first storage is instructed according to a first combination of the signals supplied to the control terminals and at least a part of the signals supplied to the address terminals, an operation of the second storage is instructed according to a second combination of the signals supplied to the control terminals and at least a part of the signals supplied to the address terminals, and a command for instructing an operation of the first storage, which is specified by a combination of the control signals supplied to the control terminals after the operation of the first storage or the operation of the second storage is instructed and a command for instructing the operation of the second storage are the same code.
Consequently, since the first and second storages having memory cells of
Dono Chiaki
Fujisawa Hiroki
Isoda Masanori
Takahashi Tsugio
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Hoang Huan
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