Designing addition circuits

Details Designing addition circuits Designing addition circuits

1999-08-16

2003-02-11

Mai, Tan V. (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

06519622

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to addition circuits for adding a binary number A to a binary number B, and more particularly but not exclusively to addition circuits designed to meet particular process or application criteria.
BACKGROUND OF THE INVENTION
A variety of different addition circuits are known. One basic example is illustrated in FIG.
1
. The binary number A is represented as a series of bits a
i
where i is the binary weight of the bit a
i
and increases from the value zero for the least significant bit of A in steps of one to the value of the most significant bit of A. The binary number B is a series of bits b
i
where i is the binary weight of the bit. The summation of the numbers A and B is represented by the binary number S which is a series of bits s
i
where i is the binary weight of the bit, and C
8
which is the msb of the sum.
The bit a
0
and the bit b
0
are supplied as inputs to an AND gate
2
0
which produces the bit generate g
0
. The bit a
0
and the bit b
0
are also supplied as inputs to an XOR gate
4
0
which produces s
0
as its output. The bit a
1
and the bit b
1
are supplied as inputs to an XOR gate
4
1
which produces the first bit propagate signal p
1
. The bit generate signal g
0
and the first bit propagate signal p
1
are supplied as inputs to an XOR gate
24
1
which produces the bit s
1
. The bit a
1
and the bit b
1
are also supplied as inputs to an OR gate
6
1
which supplies its output as a first input to an AND gate
8
1
. The second input of the AND gate
8
1
is received from the output of the AND gate
2
0
. The output of the AND gate
8
1
provides a first input to an OR gate
10
1
. The second input to the OR gate
10
1
is received from an AND gate
2
1
which receives as inputs the bit a
1
and the bit b
1
. The bit a
2
and the bit b
2
are supplied as inputs to an XOR gate
4
2
which provides its output as a first input to a XOR gate
24
2
. The second input to the XOR gate
24
2
is provided by the output of the OR gate
10
1
. The output of the XOR gate
24
2
provides the bit s
2
. The bit a
2
and the bit b
2
are also combined in an OR gate
6
2
to produce a first input to an AND gate
8
2
which receives as a second input the output from the OR gate
10
1
.
The output from the AND gate
8
2
supplied as a first input to a OR gate
10
2
. The second input to the OR gate
10
2
is supplied by a AND gate
2
2
which receives as an input the bits a
2
and b
2
. The output of the OR gate
10
2
is supplied as a first input to a XOR gate
24
3
. The second input to the XOR gate
24
3
is supplied by the output of an XOR gate
4
3
which receives as inputs the bit a
3
and the bit b
3
. The output of the XOR gate
24
3
provides the bit s
3
. An AND gate
2
3
also receives the bits a
3
and b
3
and provides its output as a first input to a OR gate
16
3
. The second input to the OR gate
16
3
is provided by an AND gate
14
3
which receives as a first input the output from the AND gate
2
2
and as a second input the output from an OR gate
6
3
which receives as inputs the bit a
3
and bit b
3
. The output from the OR gate
6
3
is also provided as a first input to an AND gate
12
3
which receives as a second input the output from the OR gate
6
2
.
The output from the AND gate
12
3
is supplied as a first input to an AND gate
8
3
which receives as a second input the output from the OR gate
10
1
. The output from the AND gate
8
3
and the output from the OR gate
16
3
are combined in an OR gate
10
3
. A XOR gate
24
4
receives as a first input the output from the OR gate
10
3
and as a second input the output from an XOR gate
4
4
which receives as inputs the bit a
4
and the bit b
4
. The XOR gate
24
4
produces the bit s
4
.
An OR gate
6
4
receives an inputs the bit a
4
and bit b
4
and provides its output as a first input to an AND gate
8
4
. The AND gate
8
4
receives as its second input the output from the OR gate
10
3
and provides its output to a OR gate
10
4
. The other input to the OR gate
10
4
is provided by an AND gate
2
4
which receives as inputs the bit a
4
and the bit b
4
. An XOR gate
24
5
produces the bit s
5
and receives as a first input the output from the OR gate
10
4
and receives as a second input the output from an XOR gate
4
5
which receives as inputs the bit as and the bit b
5
. An AND gate
12
5
receives as a first input the output from the OR gate
6
4
and an output from an OR gate
6
5
which receives as inputs the bit a
5
and the bit b
5
.
An OR gate
16
5
receives as a first input the output from an AND gate
2
5
which receives as inputs the bit as and the bit b
5
and as a second input receives the output from an AND gate
14
5
which itself receives as inputs the output from the AND gate
2
4
and the output from the OR gate
6
5
. The output from the AND gate
12
5
is combined with the output from the OR gate
10
3
in an AND gate
8
5
to produce a first input to a first OR gate
10
5
. The second input to the OR gate
10
5
is provided by the output from the OR gate
16
5
.
The output from the OR gate
10
5
is provided as a first input to the XOR gate
24
6
. The XOR gate
24
6
receives as a second input the output from the XOR gate
4
6
which receives as inputs the bit a
6
and the bit b
6
. The XOR gate
24
6
produces as an output the bit s
6
.
An OR gate
6
6
receives as its inputs the bit a
6
and the bit b
6
and supplies its output as a first input to an AND gate
12
6
. The second input to the AND gate
12
6
is supplied by the output of the AND gate
12
5
and the output of the AND gate
12
6
is supplied as a first input to an AND gate
8
6
.
The output from the OR gate
6
6
is supplied as a first input to an AND gate
14
6
. The AND gate
14
6
receives as a second input the output from the OR gate
16
5
and provides an output signal to a first input of an OR gate
16
6
. The second input to the OR gate
16
6
is supplied by an AND gate
2
6
which receives as inputs the bit a
6
and the bit b
6
. The AND gate
8
6
which receives as a first input the output from the AND gate
12
6
receives as a second input the output from the OR gate
10
3
and provides its output as a first input to an OR gate
10
6
. The second input to the OR gate
10
6
is provided by the output of the OR gate
16
6
.
The output of the OR gate
10
6
is provided as a first input to an XOR gate
24
7
. The XOR gate
24
7
receives as a second input the output from an XOR gate
4
7
which receives as inputs the bit a
7
and the bit b
7
. The XOR gate
247
produces the bit s
7
.
The bit a
7
and the bit b
7
are combined in an OR gate
6
7
to produce a first input to an AND gate
18
7
which receives as a second input the output from the OR gate
6
6
. The output from the OR gate
6
7
is supplied as a first input to an AND gate
20
7
. The AND gate
20
7
receives as a second input the output from the AND gate
2
6
. The output from the AND gate
20
7
is supplied as a first input to an OR gate
22
7
. The second input to the OR gate
22
7
is provided by a AND gate
2
7
which receives as its inputs the bit signal a, and the bit signal b
7
.
An AND gate
14
7
receives as its inputs the output from the AND gate
18
7
and the output from the OR gate
16
5
and provides its output as a first input to an OR gate
16
7
. The second input to the OR gate
16
7
is supplied by the output of the OR gate
22
7
. The output of the OR gate
16
7
is provided as a first input to an OR gate
10
7
. An AND gate
12
7
receives as its inputs the output from the AND gate
12
7
and the output from the AND gate
18
7
. The output from the AND gate
12
7
is supplied as a first input to the AND gate
8
7
. The AND gate
8
7
receives as a second input the output from the OR gate
10
3
. The output from the AND gate
8
7
is supplied as a second input to the OR gate
10
7
. The output of the OR gate
10
7
produces the last carry value c
8
.
An addition circuit that can quickly change between producing an output value A+B and output value A&p

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