Bipolar junction transistors for on-chip electrostatic...

Details Bipolar junction transistors for on-chip electrostatic... Bipolar junction transistors for on-chip electrostatic...

2002-03-12

2003-06-10

Nguyen, Tuan H. (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

C257S526000, C257S362000

Reexamination Certificate

active

06576974

ABSTRACT:

DESCRIPTION OF THE INVENTION
1. Field of the Invention
This invention pertains in general to a semiconductor device and, more particularly, to a silicon bipolar junction transistor for electrostatic discharge protection and methods thereof.
2. Background of the Invention
A semiconductor integrated circuit (IC) is generally susceptible an electrostatic discharge (ESD) event, which may damage or destroy the IC. An ESD event refers to a phenomenon of electrical discharge of a current (positive or negative) for a short duration in which a large amount of current is provided to the IC. The high current may be built-up from a variety of sources, such as the human body. Many schemes have been implemented to protect an IC from an ESD event, such as diodes or diode-coupled transistors in radio-frequency (RF) applications.
In RF applications, an on-chip ESD circuit should provide robust ESD protection, while exhibiting minimum parasitic input capacitance and low voltage-dependency. In a deep-submicron complementary metal-oxide semiconductor (CMOS) process with shallow-trench isolations (STIs), a diode has been used for ESD protection. The diode is formed contiguous with either an N
+
or P
+
diffusion region in a semiconductor substrate.
FIG. 1A
shows a cross-sectional view of a known diode ESD protection structure formed in an IC. Referring to
FIG. 1A
, a P
+
diffusion region is bound by STIs on either side, and therefore the diode is also known as an STI-bound diode. However, an STI-bound diode has been found to have significant leakage current due to an interference between a silicide layer (not shown) of the P
+
diffusion region and the STIs around the P
+
region.
FIG. 1B
shows a cross-sectional view of a known polysilicon-bound diode introduced to address the leakage current problem associated with an STI-bound diode. The P
+
diffusion region in the polysilicon-bound diode is defined by a polysilicon gate, and therefore the leakage current from the edges of STIs is eliminated. However, the total parasitic capacitance of the polysilicon-bound diode is larger than that of the STI-bound diode because of the additional sidewall junction capacitance.
FIG. 2
is a circuit diagram showing a known ESD protection scheme using a dual-diode structure. Referring to
FIG. 2
, the combination of the dual-diode structure and V
DD
-to-V
SS
ESD clamp circuit provides a path for an ESD current
2
to discharge to ground, preventing the ESD current
2
from passing through internal circuits. When the ESD current
2
is provided to a signal pad PAD
1
, and with a signal pad PAD
2
coupled to relative ground, the ESD current
2
is conducted to V
DD
through a diode Dp
1
. The ESD current
2
is discharged to V
SS
through the V
DD
-to-V
SS
ESD clamp circuit and flows out of the IC from the diode Dn
2
to the pad PAD
2
. Diode Dp
1
has a capacitance of Cp
1
and diode Dn
1
has a capacitance of Cn
1
. The total input capacitance C
in
of the circuit shown in
FIG. 2
primarily comes from the parasitic junction capacitance of the diodes, and is calculated as follows:
C
in
=Cp
1
+
Cn
1
wherein Cp
1
and Cn
1
are parasitic junction capacitances of diodes Dp
1
and Dn
1
, respectively.
In addition, a silicon-controlled rectifier (SCR) has also been implemented for on-chip ESD protection. A feature of an SCR is its voltage-holding ability, at approximately 1 volt, in a non-epitaxial bulk CMOS process. In addition, an SCR can sustain high current and hold the voltage across the SCR at a low level, and may be implemented to bypass high current discharges associated with an ESD event. However, a conventional SCR device has a switching voltage of more than 30 volts in sub-micron CMOS processes, and therefore is not suitable to protect gate oxides in a sub-micron CMOS technology.
FIG. 3
is a reproduction of FIG. 3 of U.S. Pat. No. 5,012,317 to Rountre, entitled “Electrostatic Discharge Protection Circuit.” Rountre describes a lateral SCR structure made up of a P
+
type region
48
, an N-type well
46
, a P-type layer
44
, and an N
+
region
52
. According to Rountre, a positive current associated with an ESD event flows through the region
48
to avalanche a PN junction between the well
46
and layer
44
. The current flows from the layer
44
to the region
52
across the PN junction and ultimately to ground to protect an IC from the ESD event. However, a disadvantage of this known SCR structure is its susceptibility to being accidentally triggered by substrate noise.
In addition, the p-n-p-n path of an SCR device, such as the device shown in
FIG. 3
, is blocked by the insulator layer and shallow trench isolations (STIs) in an IC formed with a silicon-on-insulator (SOI) CMOS technology. Accordingly, SCR devices have been proposed in an integrated circuit based on the SOI CMOS technology.
FIG. 4
is a reproduction of
FIG. 4
of U.S. Pat. No. 6,015,992 to Chatterjee, entitled “Bistable SCR-like switch for ESD protection of silicon-on-insulator integrated circuits.” Chatterjee describes an “SCR-like switch” provided by a first transistor
42
and a second transistor
44
, separated from each other by an insulation region
60
. The bistable SCR-like device has two additional lines
62
,
64
to electrically connect the separate transistors.
FIG. 5
is a reproduction of FIG. 8B of U.S. Pat. No. 5,754,381 (the '381 patent) to Ker, one of the inventors of the present invention. The '381 patent is entitled “Output ESD Protection with High-Current-Triggered Lateral SCR” and describes a modified PMOS-trigger lateral SCR (PTLSCR) structure and NMOS-trigger lateral SCR (NTLSCR) structure. The '381 patent describes an NTLSCR
44
modified by an addition of a parasitic junction diode Dp
2
. The '381 patent describes that the modified PTLSCR or NTLSCR structure prevents an SCR from being triggered by a substrate noise current, thereby preventing device latch-up.
SUMMARY OF THE INVENTION
In accordance with the invention, there is provided An integrated circuit device that includes a substrate, a dielectric layer disposed over the substrate, and a layer of silicon, formed over the dielectric layer, including a first portion, a second portion, and a third portion disposed between the first and second portions, wherein the first and second portions are doped with the same type of impurity, and the third portion is doped with a different type of impurity from the first and second portions, and wherein the first, second and third portions form a silicon bipolar junction transistor, the first and second portions being one of collector and emitter, and the third portion being a base of the silicon bipolar junction transistor, to provide electrostatic discharge protection to the integrated circuit device.
In one aspect, the integrated circuit device further includes an insulating layer disposed between the substrate and the dielectric layer, wherein the integrated circuit device is a silicon-on-insulator device.
In another aspect, the silicon layer includes a fourth portion disposed between the second and third portions of the silicon layer.
In yet another aspect, the silicon bipolar junction transistor includes a back-gate adapted to receive a bias voltage to control the silicon bipolar junction transistor in providing electrostatic discharge protection.
Also in accordance with the present invention, there is provided an integrated circuit device that includes a substrate having a first insulator spaced-apart from a second insulator, and a biasing region disposed between the first and second insulating regions, a dielectric layer disposed over the substrate, and a layer of silicon, formed over the dielectric layer, including a first portion, a second portion, and a third portion disposed between the first and second portions, wherein the first and second portions are doped with the same type of impurity, and the third portion is doped with a different type of impurity from the first and second portions, and wherein the first, second and thir

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