Method using a word line driver for driving a word line

Details Method using a word line driver for driving a word line Method using a word line driver for driving a word line

2002-11-07

2003-06-17

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S185230

Reexamination Certificate

active

06580658

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a method for driving a word line, and more particularly, to a method using a word line driver for driving a word line.
2. Description of the Prior Art
Flash memory is a non-volatile memory device. It has a floating gate for storing electric charges and a control gate for controlling the amount of charges stored in the floating gate. Please refer to FIG.
1
and FIG.
2
.
FIG. 1
is a functional diagram of a word line driver
10
according to the prior art.
FIG. 2
is a simplified diagram of the word line driver
10
shown in FIG.
1
. The word line driver
10
is used for driving voltages to a word line
16
. This word line
16
can be connected to control gates in devices such as flash memory so that the word line driver
10
can program or erase the flash memory.
The word line driver
10
comprises an address decoder
12
, an isolating transistor N
1
, and a level shift circuit
14
. The isolating transistor N
1
is electrically connected between the address decoder
12
and the level shift circuit
14
for isolating the address decoder
12
from the level shift circuit
14
. The level shift circuit
14
is electrically connected to the word line
16
for transmitting voltage signals to the word line
16
.
For the following explanation, 3V will represent a logical “1” and 0V will represent a logical “0” for normal operation. In order to program or erase the flash memory through the word line, however, different voltages need to be used. All voltages are supplied by positive and negative word line power sources WLP and WLN. When the flash memory is not being programmed or erased, WLP=3V and WLN=0V. However, in order to erase a flash memory cell, a positive high voltage value of 10V must be fed to the memory cell. Thus, during an erasing operation, WLP=10V and WLN=0V. On the other hand, when programming the flash memory cell, a negative high voltage value −10V must be fed to the memory cell. Thus, WLP=3V and WLN=−10V during a programming operation. These voltage values are used for simplicity in explanation, and can be changed according to specifications of the flash memory.
The address decoder
12
is used for selecting specific memory cells to program or erase. When a particular memory cell is selected to be programmed, the address decoder
12
outputs a value of 3V to the word line driver
10
corresponding to that memory cell. A gate
18
of isolating transistor N
1
is controlled to close the isolating transistor N
1
, and allow the 3V value to pass through. This 3V value then icloses transistor MN
1
, and allows the word line
16
to receive the voltage of WLN. Simultaneously, the negative word line power source is changed so that WLN=−10V. As a result, the word line
16
receives a voltage value of 10V, and is programmed properly.
An erasing operation of the word line driver works in a similar manner. To indicate that a memory cell is to be erased, the address decoder
12
outputs a value of 0V to the word line driver
10
corresponding to that memory cell. Again, the gate
18
of isolating transistor N
1
is controlled to close the isolating transistor N
1
, and allow the 0V value to pass through. This 0V value then closes transistor MP
1
, and allows the word line
16
to receive the voltage of WLP. Simultaneously, the positive word line power source is changed so that WLP=10V. As a result, the word line
16
receives a voltage value of 10V, and is erased properly.
The positive and negative word line power sources WLP and WLN are connected to many memory cells. A potential problem occurs when the value of WLP or WLN is forced to switch from regular voltage values to positive or negative high voltage values. In the programming example explained above, when the negative word line power source is switched such that WLN=−10V, this power is fed to all memory cells connected to WLN, not just the memory cell being programmed. This could cause switched voltage values to travel through the level shift circuit
14
and introduce incompatible voltage values to address decoder
12
pins corresponding to memory cells that are not being programmed. Because these incompatible voltage values could cause damage to the address decoder
12
, the isolating transistor N
1
is used to protect the address decoder
12
. Each memory cell has one isolating transistor N
1
that is selectively opened or closed in order to let voltage values pass through. Each isolating transistor N
1
is independently controlled by voltage values applied to the gate
18
of the isolating transistors N
1
.
Unfortunately, using an isolating transistor N
1
for each memory cell adds up to an enormous amount of isolating transistors used for a large array of memory cells. The use of the isolating transistor N
1
complicates circuit layout of the memory, and further leads to a more complex manufacturing process.
SUMMARY OF INVENTION
It is therefore a primary objective of the claimed invention to provide a method of using a word line driver for driving a word line, in which the word line driver does not use an isolating transistor, to solve the above-mentioned problems.
According to the claimed invention, a word line driver includes a first address decoder having a first circuit and a second circuit for selecting the word line, and a control end disposed between the first circuit and the second circuit. In addition, the word line driver has a level shift circuit connected between a first power supply, a second power supply, the first address decoder and the word line for shifting a voltage level of the word line, and the level shift circuit has an input end connected to the second circuit of the first address decoder. A method of using the word line driver for driving a word line includes shifting a voltage level of the control end while turning on the second circuit so as to shift a voltage level of the input end of the level shift circuit, and shifting a voltage level of at least one of the first and second power supplies and using the second circuit to isolate the voltage level of the control end from the voltage level of the word line.
It is an advantage of the claimed invention that the second circuit is able to isolate the voltage level of the control end from the voltage level of the word line without using a dedicated isolating transistor. This reduces manufacturing complexity, and leads to lower costs for memory production.


REFERENCES:
patent: 5602796 (1997-02-01), Sugio
patent: 6104665 (2000-08-01), Hung et al.
patent: 6370063 (2002-04-01), Kim
patent: 6535430 (2003-03-01), Oruga et al.

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