Semiconductor memory device having an echo signal generating...

Details Semiconductor memory device having an echo signal generating... Semiconductor memory device having an echo signal generating...

2001-09-04

2003-02-04

Tran, M. (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000

Reexamination Certificate

active

06515938

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-273596, filed on Sept. 8, 2000; the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates generally to a clock synchronous semiconductor memory device, and more particularly to a semiconductor memory device constructed to generate an echo signal composed of a predetermined expected value pattern, synchronizing with a clock in order to notify of a data output an external device for controlling the semiconductor memory device.
There has hitherto been known a clock synchronous semiconductor memory device in which a data I/O register takes in external data at a timing synchronizing with a clock and outputs read data at a timing synchronizing with the clock, respectively.
A higher performance of this type of clock synchronous semiconductor memory involves more reliable transfer and receipt of the data between an external device and the semiconductor memory, and hence a system for generating an echo signal synchronizing with the clock in the semiconductor memory is used.
FIG. 7
is a block diagram showing one example of this type of system. A semiconductor memory
71
is classified as, e.g., a clock synchronous SRAM. An ASIC
72
supplies input data DIN and takes in output data DOUT together with a clock CK and an address ADD. The semiconductor memory
71
outputs an echo signal ECHO composed of a predetermined expected value pattern in synchronization with the clock CK. The ASIC
72
determines an output timing of the output data DOUT by use of this echo signal ECHO.
FIG. 8
shows an operation timing of the semiconductor memory
71
shown in FIG.
7
. The address ADD is taken in synchronizing with the clock CK, and the output data DOUT is outputted likewise synchronizing with the clock CK.
FIG. 8
shows a cycle time TKC defined as one cycle of the clock CK, ad a data output time TKQV defined as a delay time till the output data DOUT is actually outputted to an I/O terminal from an edge of the clock CK (a rising edge in the case of FIG.
8
). The cycle time and the data output time are indexes for indicating a high speed performance of the semiconductor memory
71
.
For notifying the ASIC
72
for controlling the semiconductor memory
71
, of the data output time TKQV defined as a delay of the output data DOUT, the semiconductor memory
71
generates an echo signal ECHO with a delay &dgr; corresponding to the data output time TKQV in synchronism with the clock CK. In
FIG. 8
, the echo signal ECHO is shown as a simple clock signal with the clock CK delayed by &dgr; but is in fact preset as an expected value pattern composed of a predetermined combination of data of “1” and “0”.
The high speed performance of the semiconductor memory is evaluated based on how much the cycle time TKC and the data output time TKQV are decreased. The cycle time TKC and the data output time TKQV are determined as specifications in consideration of a transmission characteristic of the memory internal circuit. If this type of semiconductor memory is operated fast at a cycle time equal to or smaller than, for instance, the cycle time prescribed in the specifications, the data output time TKQV relatively increases in terms of limitations of response performance of the internal circuit.
To be specific, the consideration is given to a case where the output data register of the synchronous SRAM is set as a master/slave type. In this case, the cycle time TKC or the data output time TKQV can be improved by adjusting activation timings of the master register and the slave register.
According to this adjusting method, however, there occurs a trade-off relationship in which one of the cycle time TKC and the data output time TKQV is improved, while the other declines.
On the other hand, the delay &dgr; of the echo signal ECHO is fixed. Therefore, when operating the synchronous SRAM at the high speed, a phase difference between the data output and the echo signal occurs, and the echo generation might not sufficiently function.
This circumstance is explained ref erring to
FIGS. 9 through 11
.
FIGS. 9-11
show a relationship between the cycle time TKC and the data output time TKQV in the synchronous SRAM, wherein a cycle time TKCO and a data output time TKQVO represent data unreadable limit points delimiting areas indicated by hatching. If used with the cycle time TKC reduced down close to the limit point TKCO, as described above, the data output time TKQV declines. As a result, the phase difference between the timing of the data output and the echo signal occurs in a range A where TKC and TKQV are small as shown in FIG.
9
. This phase difference may be a cause of misreading etc.
It is required for preventing the occurrence of this phase difference between the echo signal ECHO and the data output that when actually used, as shown in, e.g.,
FIG. 10
, the limit point TKC
1
of the cycle time TKC is set to a value larger than the actual limit point TKC
0
, or alternatively, as shown in
FIG. 11
, the limit point TKQV
1
of the data output time TKQV is set larger than the actual limit point TKQV
0
. The former setting, however, leads to a sacrifice of the cycle time, while the latter setting leads to a sacrifice of the data output time.
As explained above, if the conventional synchronous semiconductor memory having the echo signal function is operated fast, the phase difference between the output data and the echo signal occurs, and the problem is that the cycle time or the data output time must be sacrificed in order to prevent this phase difference.
SUMMARY OF THE INVENTION
An echo signal generation circuit according to the present invention comprises a memory cell array; an address register for taking in an address synchronizing with a clock; a decode circuit for selecting a memory cell of said memory cell array by decoding the address retained in said address register; a reading/writing circuit for reading data from said memory cell array and writing the data to said memory cell array; a data register for temporarily retaining the data read from and written to said memory cell array, synchronizing with the clock; and an echo signal generation circuit, synchronizing with the clock, for outputting an echo signal composed of a predetermined expected value pattern for notifying the outside of a data output with a delay time equal to a transmission delay time of the output data read from said memory cell array.


REFERENCES:
patent: 5875134 (1999-02-01), Cloud
patent: 5920511 (1999-07-01), Lee et al.
patent: 5986948 (1999-11-01), Cloud
patent: 6134180 (2000-10-01), Kim et al.
patent: 6162832 (2000-12-01), Okajima

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