Classifying – separating – and assorting solids – Magnetic – Paramagnetic
Reexamination Certificate
1999-05-13
2003-02-11
Maung, Zarni (Department: 2154)
Classifying, separating, and assorting solids
Magnetic
Paramagnetic
C709S222000
Reexamination Certificate
active
06516952
ABSTRACT:
TECHNICAL FIELD
The present claimed invention relates to the field of communication devices in a network. Specifically, the present claimed invention relates to an apparatus and a method for providing a dual mode serializer-deserializer MAC-PHY level/interface for data network communication.
BACKGROUND ART
Computers and peripheral devices communicate to each other on a network through a communication port built into the device and through dedicated communication devices. Most communication port and devices utilize a seven-layered model referred to as the Open Systems Interconnection (OSI) standard that relates the digital logic signal from a device to the physical transmission medium used to transport the signal. The lower levels of the OSI relate the Media Access Control (MAC) layer and the Physical (PHY) layer. The MAC layer dictates the protocol to interpret the data communicated over a network while the PHY layer provides the physical medium used to communicate the data over the network.
The interface between the MAC and the PHY layer, e.g. the MAC-PHY interface, is important because it is essentially the first interface between the logical and the physical layers. Because it is the first layer, it's design and operation has a great effect on the balance of the system.
The PHY layer can consist of a plurality of physical channels linking two or more devices. When communicating over multiple physical channels, the MAC-PHY interface will always present a single data stream to the MAC. This can be accomplished in a number of ways. First, the multiple channels can be aggregated at a level below the MAC such that a single MAC receives a single stream of data that is aggregated from the synchronized multiple channels of data.
A conventional MAC-PHY interface for an aggregate mode of communication over a conventional multiple channel network is shown in Prior Art
FIG. 1
a.
In
FIG. 1
a,
four data channels
106
a,
106
b,
106
c
and
106
d
are respectively coupled to four serializer-deserializer devices
104
a,
104
b,
104
c,
and
104
d.
The serializer-deserializer devices, in turn, are coupled to a single MAC device
102
via channels
108
a,
108
b,
108
c,
and
108
d
that are aggregated to present a single logical channel
108
e
to the MAC device
102
. In this manner, a single data packet, e.g. packet F
110
f,
must be sent as synchronized parallel data over the multiple channels. This configuration is referred to as the aggregate mode of communication.
Alternatively, a conventional MAC-PHY interface for a non-aggregate mode of communication over a conventional multiple channel network is presented in Prior Art
FIG. 1
b.
In
FIG. 1
b,
four data channels
106
a,
106
b,
106
c
and
106
d
are respectively coupled to four serializer-deserializer devices
104
a,
104
b,
104
c,
and
104
d.
The serializer-deserializer devices, in turn, are coupled to a respective MAC device
103
a,
103
b,
103
c,
and
103
d
via channels
108
a,
108
b,
108
c,
and
108
d.
In the non-aggregate mode of communication, each of the multiple channels
108
a,
108
b,
108
c,
and
108
d
have their own separate and independent PHY and MAC devices for asynchronously communicating data. In this manner, multiple data packets, e.g. Packet A
110
a,
Packet B
110
b,
Packet C
110
c,
and Packet D
110
d,
can be sent serially across a single respective channel,
106
a,
106
b,
106
c,
and
106
d.
Consequently, this configuration is referred to as a non-aggregated transmission mode because the data is aggregated at a level above the MAC layer, and thus the MAC-PHY layer sees non-aggregate data.
Unfortunately, conventional devices are built using hardware dedicated for either synchronous aggregate communication of one packet of data over multiple channels or asynchronous non-aggregate communication of multiple packets of data over multiple channels. Thus, a device configured for one mode could not operate on a system configured for another mode. For purposes of flexibility and universal operation, a need arises for a MAC-PHY interface that can operate in both an aggregated and a non-aggregated mode.
The aggregated communication mode has the benefits of transparent operation and optimal bandwidth utilization. Furthermore, it provides the lowest amount of latency for communicating data. However, if a failure occurs on one of the channels of a device configured for an aggregate mode of communication, the whole device will fail to communicate.
Alternatively, the non-aggregate communication mode has higher latency times because each data packet is transmitted in parallel over just one of the multiple channels. However, if a failure occurs on one of the channels of a device configured for a non-aggregate mode of communication, then a higher level of logic will compensate for this failure and successfully communicate on the balance of the channels. Hence, the non-aggregate communication mode has a much higher fault tolerance than the aggregate communication mode. Thus, both the aggregate and non-aggregate mode of communication have mutually exclusive strengths and weaknesses. Consequently, a need for a device to have the benefit of communicating in the aggregate mode while no communication faults exist and communicating in the non-aggregate mode when a fault arises. More specifically, there is a need for a device to have the option to switch between modes of communication to take advantage of the strengths of both communication modes.
In summary, a need exists for a method and apparatus for a MAC-PHY interface that can operate in both an aggregated and a non-aggregated mode. Also, a need exists for a method and apparatus for a device to have the benefit of aggregate communication while having the high fault tolerance of non-aggregate communication. More specifically, a need exists for a device to have the option to switch between modes of communication so as to take advantage of the benefits of both modes. The present invention provides a unique and novel solution that meets the above needs.
DISCLOSURE OF THE INVENTION
The present invention provides a method and apparatus for a MAC-PHY interface having dual mode serializer-deserializer that can be switched.
Specifically, in one embodiment, the present invention recites a method for configuring the communication mode of a device having a Media Access Control-Physical Layer (MAC-PHY) interface for communicating with another device. One step receives a control signal at a device having a MAC-PHY Interface. The control signal indicates whether the device will communicate data over its data path in an aggregate mode or in a non-aggregate mode. In another step, the device is configured to communicate in the mode selected by said control signal. In another step, data is communicated over the data path of the device in a synchronous manner when the device is in an aggregate mode, and data is communicated over the data path of the device in an asynchronous manner when the device is in a non-aggregate mode. By having the option to operate in a plurality of modes, the present invention has a more universal application over the conventional single-mode operation. Furthermore, the present invention offers the benefits of both modes in a single method. That is, the present invention offers both the preferred, e.g. aggregate, mode of communication along with the preferred fault-tolerance, e.g. non-aggregate, mode of communication.
In another embodiment, the present invention recites a dual-mode serializer/deserializer device capable of being coupled to, and communicating with, a communication network. The device is comprised of a reference clock source, a plurality of serializer/deserializer circuits, and a clock selection circuit coupling all three elements together. Each of the serializer/deserializer circuits has its own respective clock source. The clock-selection circuit, selectively couples each of the plurality of serializer/deserializer circuits to a reference clock source. The clock-selection circuit also selectively couples each of said ser
Wang Peter
Yu Ben Yunbei
3Com Corporation
Maung Zarni
Wagner , Murabito & Hao LLP
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