Expanding microcode associated with full and partial width...

Details Expanding microcode associated with full and partial width... Expanding microcode associated with full and partial width...

1999-12-31

2003-06-17

Coleman, Eric (Department: 2183)

Electrical computers and digital processing systems: processing

Instruction decoding

Decoding instruction to accommodate variable length...

C712S001000

Reexamination Certificate

active

06581154

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to field of computer microarchitecture. More specifically, the invention relates to apparatus and methods for decoding and translating instructions that are executed within a microprocessor.
BACKGROUND OF THE INVENTION
The volume and complexity of data processed by today's personal computers are increasing exponentially, placing incredible demands on the computer's processor. New communications, games and “edutainment” applications feature video, 3D graphics, animation, audio and virtual reality, all of which demand ever-increasing levels of performance.
In light of the demands placed upon the processor, a technology called Single Instruction, Multiple Data (SIMD) was developed. This technology allows many pieces of information, or data elements, to be processed with a single instruction, providing parallelism that greatly increases performance.
To better appreciate the problem faced by researchers working in the field of computer design and architecture, one must first understand the basics of how instructions are processed within the machine. The architecture of many processors implement programmed instructions—often referred to as macro-instructions—by sequences of coded statements. In order for a macro-instruction to be acted on by the processor, it must be decoded into a sequence of micro-instructions or micro-operations (conveniently termed “micro-ops” or “uops”) that can be executed by the processor's core logic.
The Katmai New Instruction Set (KNI), a processor instruction set developed by Intel Corporation, the assignee of the present invention, combines SIMD processing and the aforementioned use of macro-instructions. The underlying hardware implementation of a Katmai processor facilitates parallel operation on two sets of data elements simultaneously. KNI instructions, therefore, have packed, as well as, scalar versions of various operations. A scalar operation being one that operates on a single set of elements at a time, and a packed operation being one in which two or more sets of data elements are acted upon simultaneously. For example, In a packed version of the “add” instruction, multiple data elements of the two input operands may be added in parallel; whereas, in the scalar version of the “add” instruction, only one data element of each of the input operands is added at a time.
SIMD processing greatly increases processing speed by allowing multiple sets of data to be operated on simultaneously. It does carry the risk of increasing the amount of instruction translation information that must be stored by the processor in micro code ROM (also “ucode ROM” and “UROM”). For example, a uop for the scalar “Add” operation and another for the packed “Add” operation may need to be stored in the UROM. The requirement of larger UROM results in potentially greater fabrication costs and the larger UROM hinders the ability of the decoding process to be run at higher frequencies.
SUMMARY OF THE INVENTION
A method of processing data to multivariate instructions is disclosed and described herein. First, a macro-instruction for processing a particular set of data is decoded into a special micro-operation (micro-op). The special micro-op comprising a code sequence that is generic with regard to a set of multiple variant macro-instructions. An indicator associated with the special micro-op is also generated. The indicator indicates a particular variant of the set of multiple variant macro-instructions. Next, using the indicator, the special micro-op is converted into one or more micro-ops containing a code sequence that will perform the particular variant of the set of multiple variant macro-instructions as specified by the macro-instruction.


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