Radiant energy – Photocells; circuits and apparatus – Photocell controlled circuit
Reexamination Certificate
2001-05-14
2003-12-16
Pyo, Kevin (Department: 2878)
Radiant energy
Photocells; circuits and apparatus
Photocell controlled circuit
C257S444000, C358S483000
Reexamination Certificate
active
06664527
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a photoelectric converter, and in particular, to a two-dimensional photoelectric converter that is used for facsimile machines, digital copy machines, and X-ray machines.
2. Related Background Art
Conventionally, a scanning system that employs a reducing optical system and a CCD sensor is used for a scanning apparatus, such as a facsimile machine or a digital copy machine. Recently, however, as a consequence of the development of photoelectric conversion semiconductor material, such as amorphous silicon (hereinafter referred to as a-Si), a so-called close-contact sensor has been developed for which a photoelectric conversion device and a signal processor are formed on a large substrate, and by which data are scanned by using an optical system that has the same magnification rate as that of a data source. Furthermore, since a-Si can be employed not only as a photoelectric conversion material but also as a thin film field-effect transistor film (hereinafter referred to as a TFT), both a photoelectric conversion semiconductor layer and a TFT semiconductor layer can be formed at the same time.
The basic structure of a photoelectric converter that uses a-Si is described in the specification for U.S. Pat. No. 4,376,888, or in Japanese Patent Publication No. 62-23944, or Japanese Patent Publication No. 63-6617.
A specific example for the integral forming of an a-Si photosensor and an a-Si TFT is described in the specifications for U.S. Pat. No. 4,931,661, U.S. Pat. No. 5,338,690 and U.S. Pat. No. 5,306,648.
Based on the techniques disclosed in these specifications, the present inventors produced as a sample photoelectric converter a two-dimensional area type in which the number of pixels was drastically increased. The outline of the photoelectric converter will now be described while referring to
FIGS. 1 and 2
. This device is disclosed in European Patent Publication No. 0660421.
FIGS. 1 and 2
are plan views of a photoelectric converter that has 2000×2000 pixels. To provide 2000×2000 sensors, the number of photoelectric conversion devices that are included in an arrangement are increased in both the vertical and the horizontal directions. For this converter, 2000 control lines (scan lines) are also required, as is indicated by g
1
through g
2000
, and accordingly, 2000 signal lines (data lines) are required, as is indicated by sig
1
through sig
2000
. In addition, the sizes of a scanning circuit and an integrated circuit used for detection (a detection IC) are increased because they have to control and handle 2000 signal lines. When these processes are performed by single, one-chip ICs, the sizes of the chips must be increased, and the yielding manufacturing ratio and the prices are adversely affected. As is shown in
FIGS. 1 and 2
, in a scan circuit, therefore, sufficient shift registers to handle 100 stages, for example, are formed on a single chip and 20 of these scan circuit chips (SR
1
-
1
through SR
1
-
20
) are used. For the detection process for the integrated circuit, 100 processing circuits are formed on a single chip, and 20 of these integrated circuit detection chips (IC-
1
through IC-
20
) are used.
In
FIG. 1
, 20 chips (SR
1
-
1
through SR
1
-
20
) are mounted along the left side (L) and another 20 chips (IC-
1
through IC-
20
) are mounted across the down side (D). Connected to each chip by wire bonding are 100 control lines or signal lines. The portion that is enclosed by broken lines in
FIG. 1
corresponds to a photoelectric conversion device array that is arranged as a two-dimensional area. The connection of the detection integrated circuit to an external device is not shown.
In another example, shown in
FIG. 2
, 10 chips (SR
1
-
1
through SR
1
-
10
) are mounted along the left side (L) and 10 chips (SR
1
-
11
through SR
1
-
20
) are mounted along the right side (R); and 10 chips (IC-
1
through IC-
10
) are mounted across the upper side (U) and 10 chips (IC-
11
through IC-
20
) are mounted across the down side (D). Since in this structure 1000 lines are provided at each of the upper, down, left and right sides (U, D, L and R), the density of the lines arranged along each side is reduced and the concentration of the wire bonding required on each side is also decreased, thus providing an increased manufacturing yielding ratio. Lines g
1
, g
3
, g
5
, . . . , and g
1999
are arranged along the left side (L), while g
2
, g
4
, g
6
, . . . , and g
2000
are arranged along the right side (R). That is, the odd numbered control lines are distributed along the left side (L), and the even numbered control lines are distributed along the right side (R). With this arrangement, since each line is pulled out so that the lines are located at equal intervals, the lines are not overly concentrated and the yielding ratio is increased. The wiring across the upper side (U) and the down side (D) is performed in the same manner.
Though not shown, in an additional example, lines g
1
through g
100
, g
201
through g
300
, . . . , and g
1801
through g
1900
are provided on the left side (L), while lines g
101
through g
200
, g
301
through g
400
, . . . , and g
1901
through g
2000
are provided on the right side (R). In other words, it is possible for continuous control lines to be distributed to each chip and for these chips to be alternately sorted to the left side and to be right side (to L and to R). With this arrangement, the control lines for a single chip can be controlled sequentially, the adjustment and the setup of drive timing can be facilitated, a circuit does not become complicated, and an inexpensive IC can be used. The same arrangement can be applied for upper and the down sides (U and D), and an inexpensive IC that can perform a continuous process can be used.
During the manufacturing process for a photoelectric converter having large dimensions, however, it is difficult to completely remove minute dust particles; it is especially difficult to remove a contaminant that is peeled off the wall of a thin film deposition device before a semiconductor layer, such as an amorphous layer, is deposited on a substrate, and it is also difficult to remove dust that remains on a substrate before a metal layer is deposited on the substrate. Therefore, it is difficult to eliminate wiring defects, i.e., short circuits or open circuits in lines.
When the short circuits or open circuits in the control lines or the signal lines occur in a photoelectric converter having large dimensions, all of the output signals of the photoelectric converter devices that are connected to the short-circuited are rendered inexact, and the converter can not function as a photoelectric converter.
In other words, as the size of one substrate is increased for the fabrication of a photoelectric converter having large dimensions, losses due to defects that occur during the manufacture of a substrate are also increased.
Further, if the selection of control lines (scanning) is so designed that it is performed in the order corresponding to the direction indicated by arrow AL
1
in
FIG. 2
, the order in which the output terminals for each of the scan circuits SR
1
-
1
through SR
1
-
10
are arranged on the left side (L) in
FIG. 2
is the opposite of the order in which the output terminals for each of the scan circuits SR
1
-
11
through SR
1
-
20
are arranged on the right side (R). When the scan circuits that are arranged on both sides are formed by using IC chips having the same structure, connection lines (lines for connecting control lines to the output terminals of the scan circuits) on either the right side (R) or the left side (L) must be formed of multi-layer lines, etc. As a result, the structure of the connection lines becomes complicated and expensive, and the high-density mounting of scan circuits is prevented.
Two types of ICs are prepared for which the orders in which output terminals are located differ, and ICs of one type are arranged on the left side (L), while ICs of the other type a
Endo Tadao
Kaifu Noriyuki
Kameshima Toshio
Kobayashi Isao
Takeda Shinichi
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