Semiconductor device manufacturing: process – With measuring or testing – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2002-10-08
2003-10-07
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
With measuring or testing
Packaging or treatment of packaged semiconductor
C438S107000, C438S685000
Reexamination Certificate
active
06630365
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to structures for spacing a semiconductor device, such as a ball grid array (BGA) package or a flip-chip type semiconductor die, a desired distance from a carrier substrate. The structures of the present invention are also useful for providing stability to the semiconductor device during and following mounting thereof to a carrier substrate. More specifically, the invention pertains to stereolithographically formed spacer structures and to the use of stereolithographic methods to fabricate the spacer structures.
Flip-Chip Dice and Ball Grid Array Packages
2. State of the Art
Flip-chip technology, including ball grid array packaging technology, is widely used in the electronics industry. In both the generic flip-chip and the ball grid array technologies, a semiconductor device having a pattern of conductive pads on an active surface thereof is joined face down to a higher level substrate, such as a printed circuit board. The contact pads of the higher level substrate are arranged in a mirror image to corresponding contact pads on the semiconductor device. Conductive structures, typically solder bumps (as exemplified by the so-called C-4 technology), conductive epoxy bumps or pillars, conductor-filled epoxy, or an anisotropically z-axis conductive elastomer, are used to join contact pads on the surface of the semiconductor device with their corresponding contact pads on the higher level substrate, establishing electrical communication between the semiconductor device and the higher level substrate.
When the semiconductor device is a flip-chip type semiconductor die, the spacing or pitch between adjacent contact pads, or bond pads, is relatively small. The contact pads themselves are also very small. State of the art flip-chip type semiconductor dice typically include many contact pads in an array on the active surfaces thereof. The high density, small feature size, and large number of conductive pads on state-of-the-art semiconductor dice make the disposal of uniformly sized and configured conductive structures thereon a challenging process. Relatively small variations in the size or shape of the conductive structures can be accommodated for during bonding of the conductive structures to the contact pads of the higher level substrate. However, due to larger dimensional variations in the conductive structures on flip-chip type semiconductor dice, higher bonding temperatures or compressive forces are typically required to ensure the formation of adequate bonds between the bond pads of a flip-chip type semiconductor die and the corresponding contact pads of a higher level substrate. The use of higher temperatures can damage the circuitry and other features of the semiconductor die, as well as impair the integrity of the conductive structures. Overcompression of the conductive structures can also be detrimental. When a compressed conductive structure spreads over and contacts the glass (e.g., borophosphosilicate glass (BPSG), borosilicate glass (BSG), or phosphosilicate glass (PSG)) passivation layer that typically surrounds the bond pads of a semiconductor die, thermal cycling of the semiconductor die during subsequent processing or in use can fracture the conductive structure and diminish the electrical conductivity thereof.
FIG. 4
illustrates overflattened solder bumps
220
A. Such overflattening may occur when solder bumps
220
are subjected to overly high temperatures when there are an inadequate number of bumps (see below for further explanation), or when a compressive force
222
,
224
is applied to die
200
to ensure the formation of adequate electrical connections between each bond pad
202
of die
200
and its corresponding contact pad
230
of a carrier substrate
210
. Where flattened solder bump
220
A extends laterally beyond bond pad
202
onto a surrounding glass passivation layer
236
, thermal cycling can crack the solder at locations overlying passivation layer
236
and disrupt the electrical continuity between bond pads
202
and their corresponding contact pads
230
. It is also desirable to form solder connections with a minimum bump height for enhanced reliability, a relatively taller solder column providing a more reliable connection over time than a squat or flattened bump.
Moreover, some semiconductor dice have bond pads that are positioned in locations that will not adequately and stably support these dice when conductive structures are secured thereto and the dice are disposed face down (i.e., in a flip-chip orientation) over a higher level substrate. Examples of such dice include leads over chip (LOC)-configured semiconductor dice with one or two rows of bond pads along a central axis of the dice and semiconductor dice with bond pads positioned adjacent only a single peripheral edge thereof. Thus, when conductive structures are secured to the bond pads of such a semiconductor die and the semiconductor die is then positioned face down relative to a higher level substrate, the die is prone to being tipped or tilted from an intended orientation that is substantially parallel to a plane of the contact pad-bearing surface of the higher level substrate. As a consequence, such dice are thought to be unsuitable for flip-chip applications without rerouting of the bond pads to a more stable arrangement. In addition, one or two rows of bond pads bearing solder bumps may not exhibit sufficient surface tension to support the die during reflow of the solder, resulting in collapse or flattening of the molten solder masses and shorting of adjacent connections. Inadequate support strength may also be a problem when other conductive materials are used.
State of the art ball grid array packages, including so-called “chip-scale” packages (CSPs), also have numerous densely packed features of small sizes and are, therefore, susceptible to many of the same connection problems described above in reference to other flip-chip type semiconductor dice.
FIG. 1
illustrates an LOC-configured semiconductor die
200
having two centrally located rows of bond pads
202
on an active surface
204
thereof. The two rows of bond pads
202
are located between opposite side edges
206
and
208
of die
200
and extend generally parallel to side edges
226
and
228
. Die
200
can be flip-chip connected to a higher level substrate, in this case a carrier substrate
210
. Carrier substrate
210
has contact pads
230
exposed at a surface
214
thereof. When die
200
is assembled with carrier substrate
210
in a flip-chip type arrangement, as shown in
FIG. 2
, die
200
is to be inverted relative to carrier substrate
210
, with bond pads
202
being aligned with their corresponding contact pads
230
.
Bond pads
202
are typically connected to their corresponding contact pads
230
by way of conductive structures disposed between bond pads
202
and contact pads
230
. The conductive structures illustrated in
FIGS. 1-7
are solder bumps
220
. Typically, solder bumps
220
are first joined to bond pads
202
, die
200
is then inverted relative to carrier substrate
210
, and finally solder bumps
220
are secured to contact pads
230
by heating the solder to reflow, followed by cooling. As indicated in
FIG. 2
, the interposition of conductive bumps
220
between bond pads
202
and contact pads
230
ideally causes die
200
to be spaced apart from carrier substrate
210
a certain die-to-substrate distance
218
.
As noted previously and illustrated in
FIG. 3
, since bond pads
202
are arranged on active surface
204
in centrally located rows, die
200
is unstable and may tip or tilt relative to carrier substrate
210
. Such tipping or tilting can occur during assembly of die
200
with carrier substrate
210
or during bonding of solder bumps
220
to contact pads
230
if die
200
is not held securely in place by pick and place equipment. Tipping or tilting can also occur after die
200
and carrier substrate
210
have been assembled and solder bumps
220
have been secured b
Farnworth Warren M.
Wood Alan G.
Lebentritt Michael S.
Micro)n Technology, Inc.
TraskBritt
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