Multiplex communications – Fault recovery – Bypass an inoperative switch or inoperative element of a...
Reexamination Certificate
1999-05-20
2003-12-23
Kizou, Hassan (Department: 2662)
Multiplex communications
Fault recovery
Bypass an inoperative switch or inoperative element of a...
C370S221000, C370S225000, C370S395100
Reexamination Certificate
active
06667955
ABSTRACT:
CROSS-REFERENCED TO RELATED PATENT APPLICATIONS
The following European Patent application numbers are cross-referenced:
European patent application no. 97480057.5 filed on Aug. 19, 1997 entitled “Switching System Comprising Distributed Elements Allowing Attachment to Line Adapters, and Having Multicasting Capabilities” describes the detail of the techniques used for building large Switching architectures with sophisticated SCAL elements.
European application no. 97480056.7.
European application no. 97480065.8.
European application no. 96480129.4.
European application no. 96480120.3.
European application no. 98480039.1, filed on May 29, 1998 and entitled “Switching Architecture Comprising Two Switch Fabrics”.
European Application no. 97480100.3, from A. Blanc et al., filed on Dec. 30, 1997, and entitled “Port Expansion Architecture for Large Cell Switch”.
European Application no. 97480098.9, from A. Blanc et al., filed on Dec. 30, 1997, and entitled “Process for Transporting and Routing a Cell in a Switching Structure Based on a Single Storage Switch”.
European Application no. 97480101.1, from A. Blanc et al., filed on Dec. 30, 1997, and entitled “Congestion Management in Very Large Switching Fabrics”.
European Application no. 97480099.7, from A. Blanc et al., filed on Dec. 30, 1997, and entitled “Optional Back Pressure in ATM Switching Fabric”.
European Application no. 98480007.8, from A. Blanc et al., filed on Feb. 19, 1998, and entitled “Flow Control Process for a Switching System, and System for Performing the Same”.
European Application no. 98480006.0, from A. Blanc et al., filed on Feb. 19, 1998, and entitled “Flow Control Process for a Switching Architecture Using an Out-of-Band Flow Control Channel, and Apparatus for Performing the Same”.
European Application no. 98480039.1, from A. Blanc et al., filed on May 29, 1998, and entitled “Switching Architecture Comprising Two Switch Fabrics” discloses a switch-over when a maintenance operation is planned in one component of the active Switch over.
European Application no. 98480040.9, from A. Blanc et al., filed on May 29, 1998, and entitled “Fault Tolerant Switching Architecture” discloses a second case of switch-over that is arranged when a breakdown condition occurs in one Switch Fabric.
1. Field of the Invention
The invention relates to switching systems and, more particularly, to a Switch Fabric system which comprises at least one Switch Fabric subsystem including a set of Switch core elements being arranged in port expansion architecture.
2. Background Art
Shared buffer switches have been shown to be of great interest for switching small packets of data and well adapted to the switching of Asynchronous Transfer Mode (ATM) cells although they are not limited to the ATM technology. Basically, a shared buffer switch comprises a cell storage which is used for storing the cells which are entering through one input port of the switch. An appropriate mechanism is used for extracting the cell from the shared buffer and for directing the latter to one or more output ports of the switch. By using different output queues, each one dedicated to one output port of the switch, it is made possible to achieve a very simple multicasting effect in the switching process. Additionally, the provision of Switch Core Access Layer (SCAL) elements combined with a centralized switching system, the SCAL being located remote, allows an increasing traffic to be transported through the latter.
The high speed requirements of switching systems—resulting of a huge amount of these small cells to be switched per period—tend to force the known technology well beyond its possibilities and physical limits. Special arrangements had to be designed for going beyond the physical limit of the today technology. This was basically achieved by expanding the switching architecture in three directions.
A first way is what is known under the concept of speed expansion which allows an effective combination of several distinctive individual switching modules together; e.g., four modules, in order to form an aggregate high-rate Switching structure or Switch Core. To achieve this, the cell is divided in separate Logical Units (LU) and each one is directed to one switching module. By means of an appropriate mechanism, the four modules can be coupled and synchronized under the control of a master module which permits simultaneous routing of the four LUs towards the same destination port. This obviously permits increasing the overall switching speed, although the semiconductor technology remains unchanged.
These documents disclose the internal control of the different modules by a single master module in accordance with a bit map value introduced in the cell when the latter arrives into the switch core. The particular value that is introduced is extracted from a Routing Control Table that is associated with the master switching module.
In addition to the speed-expansion direction, the port expansion is another direction for an effective combination of individual modules in order to extend, to compensate the physical limitations of a given technology. An example of a port expansion architecture which permits multiplying the number of Port Adapters by two is shown in
FIG. 1. A
combination of four different Switching Structures or Switch Cores
111
,
112
,
121
and
122
(each one possibly comprising four switching modules if speed expansion is applied) which are arranged so as to allow the attachment of two sets of Protocol Adapters (PA). Assuming, for instance, that the number of input and output ports is fixed to 16, the port expansion architecture allows a first set of sixteen Protocol Adapters
1
-
1
to
1
-
16
and a second set of sixteen Protocol Adapters
2
-
1
to
2
-
16
to be connected to the Switch Fabric. More particularly, the input ports i of Switch Cores
111
and
112
are connected together by means of a fan-out circuit
110
-
i
in order to receive the same flow of cells coming from Protocol Adapter
1
-
i
(and, more particularly, the Receive part of the latter). Similarly, Protocol Adapter
2
-
i
produces cells which are transported via the SCAL receive part.
For the sake of clarity, only one port is represented in
FIG. 1
which shows that Switch cores
111
and
112
have an input port i that receives the cells coming from the receive part of Protocol Adapter
1
-
i
and transported via SCAL_Receive element
11
-
i
, serial long distance transmission link
13
-
i
and fan-out circuit
110
-
i
. Similarly, Switch cores
121
and
122
has an input port i that receives the cells coming from the receive part of Protocol Adapter
2
-
i
and transported via SCAL_Receive element
21
-
i
, long distance serial transmission link
23
-
i
and fan-out circuit
120
-
i.
With respect to the output ports of the switch cores, and particularly for output port j, the figure shows that Switch cores
111
and
121
are connected to the Xmit part of Protocol Adapter
1
-
j
via fan-in circuit
131
-
j
, long distance serial transmission link
13
-
j
and SCAL Xmit element
11
-
j
. Similarly, Switch cores
112
and
122
are connected to the Xmit part of Protocol Adapter
2
-
j
via fan-in circuit
132
-
j
, long distance serial transmission link
23
-
j
and SCAL Xmit element
21
-
j
. Long distance serial transmission links
13
-
i
,
23
-
i
,
13
-
j
and
23
-
j
are optical or cables that are adapted to the transmission of data rates at high speeds so that Protocol Adapters located at different areas, up to several hundreds of meter, can be attached to the centralized port expansion switching architecture. A known communication link can be found in document “Single-chip 4×500 Mbaud CMOS Transceiver” from A. Widmer et al, in IEEE ISSCC96, Session 7. ATM/SOMET/PAPER FA7.7. Published on Feb. 9, 1996 for providing 1.6 Gigabit/s communication links. When the Switch Core comprises four individual Switching modules arranged in speed expansion, link
13
-
i
comprises a set of four different serial links that are separately assigned to the transport of one dedica
Blanc Alain
Gohl Sylvie
Kaplan Menahem
Pinzaglia Alain
Cockburn Joscelyn G.
Kizou Hassan
Munoz-Bustamante Carlos
Odland David
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