Residual offset correction method and circuit for chopper...

Details Residual offset correction method and circuit for chopper... Residual offset correction method and circuit for chopper...

2002-04-16

2003-10-28

Choe, Henry (Department: 2817)

Amplifiers

With periodic switching input-output

C330S051000, C330S069000, C327S124000

Reexamination Certificate

active

06639460

ABSTRACT:

FIELD OF INVENTION
The present invention relates to operational amplifiers. More particularly, the present invention relates to a technique and circuit for providing residual offset correction in a chopper stabilized amplifier circuit.
BACKGROUND OF THE INVENTION
The demand for improved operational amplifiers, and in particular instrumentation amplifier circuits for high-precision data acquisition and instrumentation applications, such as multi-channel data acquisition systems, current shunt monitors, and industrial or physiological sensors, continues to increase. Instrumentation amplifier circuits are generally designed to amplify the difference between two voltage inputs with a defined gain, wherein a single-ended output is provided which is referenced to a known reference point, for example, ground.
Such operational amplifier circuits generally include an input stage circuit and an output stage circuit comprised of various amplifier devices and other current sources. To facilitate the reduction of error caused by mismatch of transistor devices within the various amplifier and/or current sources, operational amplifier circuits are being configured with chopper stabilization. In this technique, a pair of commutating switch blocks can be configured at the input and output of an input stage circuit in a manner to zero the voltage offset of the input stage. During operation, the switching block is configured to reverse the polarity of an input offset voltage during alternating phases, which operates to stabilize the voltage offset of the input stage. In addition, chopper stabilization can also reduce input referred low frequency noise.
For example, with reference to
FIG. 1
, an operational amplifier circuit
100
configured with chopper stabilization is illustrated. Amplifier circuit
100
includes an input stage
102
and an output stage
104
configured with a feedback arrangement
110
. Input stage
102
includes an input pair of transistors M
1
and M
2
configured to receive the input voltage, and a second pair of transistors M
A
and M
B
and a third pair of transistors M
C
and M
D
configured to provide output terminals V
O1
and V
O2
.
To facilitate the chopper stabilization process, amplifier circuit
100
includes a switching block
106
at the input of input stage
102
and a switching block
108
at the output of input stage
102
. Switching block
106
is configured to receive a differential input voltage at two input terminals, V
1
and V
2
, and through the use of two paths as determined by the closure of the switches during a first phase and a second phase, to chop the input signal at a desired chopping frequency. Switching blocks
106
and
108
are configured for modulation of the input offset voltage to provide for the reduction of offset errors due to input stage
102
. Although not shown, a common-mode feedback loop is used for a differential output configuration of input stage
102
.
For example, during a first phase, i.e., when switches designated as A are opened and switches designated as B are closed, an input voltage at V
1
crosses over through one of the B switches to the gate of input transistor M
2
, while an input voltage at V
2
crosses over through another of the B switches to the gate of input transistor M
1
. As a result, the input voltage at V
1
ends up at output terminal V
O1
, and through closure of the B switches in switching block
108
, at the positive terminal of output stage
104
, while the input voltage at V
2
ends up at output terminal V
O2
, and thus at the negative terminal of output stage
104
.
During a second phase, i.e., when switches designated as B are opened and switches designated as A are closed, the input voltage at V
1
passes through one of the A switches to the gate of input transistor M
1
, while the input voltage at V
2
passes through another of the A switches to the gate of input transistor M
2
. As a result, the input voltage at V
1
ends up at output terminal V
O2
, and through closure of the A switches in switching block
108
, again at the positive terminal of output stage
104
, while the input voltage at V
2
ends up at output terminal V
O1
, i.e., again at the negative terminal of output stage
104
.
Accordingly, while the differential input voltage, i.e., the voltage difference at terminals V
1
and V
2
, can be suitably provided to the input terninals of output stage
104
, an input offset voltage V
OS1
, occurring from input stage
102
can be suitably chopped out by switching blocks
106
and
108
.
Another characteristic of input stage
102
is the inclusion of parasitic capacitances at the output that can be the source of additional offset error. For example, input stage
102
can include a parasitic capacitance C
P1
at output terminal V
O1
and a parasitic capacitance C
P2
at output terminal V
O2
. For simplicity, a dual supply configuration is illustrated for input stage
102
. During the first phase, an offset voltage V
OS2
of output stage
104
can comprise, for example, a one millivolt signal at the positive input terminal, i.e., at output terminal V
O1
, and a zero volt signal at the negative input terminal, i.e., at output terminal V
O2
. Thus, an offset voltage V
OS2
of one millivolt can occur differentially between parasitic capacitances C
P1
and C
P2
.
However, during the second phase, the polarity of offset voltage V
OS2
occurring differentially between parasitic capacitances C
P1
and C
P2
is switched, resulting in a voltage change across parasitic capacitances C
P1
and C
P2
. As a result of this voltage change, current will flow out of parasitic capacitances C
P1
and C
P2
and into transistors M
A
and M
B
. Due to the feedback configuration, the current resulting from the voltage change will then flow to input transistors M
1
and M
2
, which have some input transconductance g
m
, and will result in additional DC offset voltage that is not chopped out by the chopper stabilization switching blocks
106
and
108
. In other words, a residual DC offset term results from a change in voltage at the output of input stage
102
, due to offset voltage V
OS2
reacting with parasitic capacitances C
P1
and C
P2
, that is not corrected by current chopper stabilization techniques. In addition, the input offset voltage increases at higher chopping frequencies, i.e., the faster the operation of switching blocks
106
and
108
, the more current that flows to input transistors M
1
and M
2
, and the greater the DC offset error that exists. Thus, while amplifier circuit
100
can provide suitable chopper stabilization at low switching frequencies, significant input offset error occurs at higher switching frequencies.
Accordingly, a need exists for a offset correction technique for residual offset occurring in chopper stabilized amplifiers.
SUMMARY OF THE INVENTION
The method and circuit according to the present invention addresses many of the shortcomings of the prior art. In accordance with various aspects of the present invention, a circuit and technique are provided that facilitate residual offset correction during chopper stabilization of an operational amplifier circuit.
In accordance with an exemplary embodiment, a chopper stabilized operational amplifier can be configured with an additional gain stage configured between input and output stages of the operational amplifier. In this exemplary embodiment, instead of a second switching block being configured on the output of the input stage, the second switching block is coupled to the output of the additional gain stage. As a result, any input offset voltage of the additional gain stage appears across the output of the input stage with the same polarity during chopper stabilization. Thus, the offset voltage that appears across the output of the input stage remains constant at the end of each of the chopping phases. Accordingly, any residual offset voltage, for example that due to changes in voltage across parasitic capacitances on the output of the input stage, can be eliminated.
In accordance with another exemplary embodiment, a feedfo

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