Television – Receiver circuitry
Reexamination Certificate
2000-08-07
2003-12-30
Lee, Michael H. (Department: 2614)
Television
Receiver circuitry
C375S345000, C375S321000
Reexamination Certificate
active
06671002
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a VSB receiver, and more particularly, to a VSB receiver for receiving a terrestrial digital broadcasting signal which is subjected to vestigial side-band (VSB) modulation and is transmitted.
BACKGROUND ART
In recent years, in the video broadcasting field, the broadcasting form has been changing from an analog form to a digital form in order to provide a high-quality video to a viewer, as is well known. The broadcasting is being digitized with respect to not only broadcasting by a satellite wave which has already been partially put to practical use but also broadcasting by a ground wave. In the United States and Europe, for example, the digitization of broadcasting by a ground wave is being currently put to practical use.
As a digital modulation system used in terrestrial digital broadcasting, various systems have been currently devised. As one of the systems, the ATSC (Advanced Television System Committee) standard for subjecting a signal to multi-valued VSB (octal VSB or hexadecimal VSB) modulation and transmitting the modulated signal has been employed in the United States.
A receiver for receiving the terrestrial digital broadcasting is feasible by being constructed similarly to a receiver basically employed in satellite digital broadcasting or the like, provided that it performs digital demodulation corresponding to digital modulation to which a signal has, been subjected. With respect to a receiver for receiving a signal which has been subjected to multi-valued VSB modulation (hereinafter referred to as a VSB receiver), a general I configuration is described in a document entitled “GUIDE TO THE USE OF THE ATSC DIGITAL TELEVISION STANDARD (Doc. A/54)” issued by ATSC.
FIG. 20
illustrates an example of the configuration of a VSB receiver described in the above-mentioned document issued by ATSC. In
FIG. 20
, the VSB receiver described in the document comprises a tuner
201
, a digital demodulation portion
202
, a waveform equalizer
203
, an error-correcting circuit
204
, a transport decoder
205
, a video decoder
206
, and an audio decoder
207
.
The tuner
201
receives a signal which has been subjected to VSB modulation. The digital demodulation portion
202
subjects the signal received by the tuner
201
to digital demodulation, and converts the received signal into a digital video signal. The waveform equalizer
203
corrects the distortion or the like of a signal waveform which occurs in a transmission path or the like. The error-correcting circuit
204
subjects the signal waveform whose distortion or the like has been corrected to error correction. The transport decoder
205
separates a video signal and an audio signal which have been transmitted in multiple. The video decoder
206
decodes the separated video signal. The audio decoder
207
decodes the separated audio signal.
It is generally considered that an automatic gain control (hereinafter denoted by an AGC) circuit and a clock regenerating circuit which are indispensable in processing a signal are naturally included as constituent elements in the digital demodulation portion
202
, which is not written clearly in the VSB receiver shown in FIG.
20
.
The AGC circuit is a circuit whose gain is controlled by a negative feedback loop such that the amplitude of a predetermined reference signal always enters a predetermined level in order to eliminate the effect of the attenuation or the like of a signal on the transmission path, as is well known. Further, the clock regenerating circuit is a circuit whose gain is controlled by a negative feedback loop such that the clock frequency of the received signal and the clock frequency of the receiver coincide with each other (synchronized) in order to regenerate a clock for giving judgment timing of each data (symbol) of a digital signal as is well known.
Each of the AGC circuit and the clock regenerating circuit is operated in order to cause a signal to be controlled to converge into a predetermined value by the negative feedback loop. Accordingly, the loop gain of each of the circuits affects a time period required until the convergence processing is completed, that is, a time period required from the time when a video signal is received until a video is outputted onto a screen. Therefore, the loop gain of each of the AGC circuit and the clock regenerating circuit is fixed to a most suitable value previously determined at which the convergence processing is performed at high speed and accurately.
Meanwhile, the terrestrial digital broadcasting differs from satellite digital broadcasting in that it is necessary to consider that a ghost disturbance is created in the transmission path. Against the ghost disturbance, it is considered that in the above-mentioned VSB receiver, the effect of a ghost can be removed in the processing in the waveform equalizer
203
.
When it is considered that the AGC circuit and the clock regenerating circuit are included in the configuration of the VSB receiver, however, the following problems arise depending on a method of setting the loop gain of each of the circuits.
First, consider a case where the loop gain of the AGC circuit is set to a large value.
In this case, the speed of AGC processing following a feedback signal is increased, so that the loop gain of the AGC circuit converges at high speed. In this case, however, the value of the result of AGC detection (an AGC voltage) is liable to be changed. When a ghost disturbance exists in the received signal, therefore, the result of the AGC detection is changed by a ghost component. Therefore, an error occurs in signal processing in the waveform equalizer
203
in the succeeding stage, resulting in a degraded ghost removal capability.
The configuration of the waveform equalizer
203
described in the above-mentioned document is taken as an example, to describe the cause of errors occurring in the signal processing in the above-mentioned case.
FIG. 21
is a block diagram showing the configuration of the waveform equalizer
203
described in the above-mentioned document.
FIG. 22
is a diagram for explaining the reason why judgment in the waveform equalizer
203
is erroneous.
The waveform equalizer
203
calculates an error signal on the basis of an output of a feedback filter and an output passing through a slicer, and calculates each filter coefficient on the basis of the error signal. The filter coefficient is gradually changed such that a ghost is removed, and the value is hardly changed after the ghost is removed. That is, the waveform equalizer
203
calculates a filter coefficient on the basis of an error between each data and a reference value in a region including the data. Consequently, the waveform equalizer
203
calculates, with respect to data in a +5 region (&Circlesolid; mark in FIG.
22
), an error between the data and the value of +5, and calculates a filter coefficient on the basis of the error. When data originally existing in the +5 region is moved into a +7 region (▾ mark in
FIG. 22
) by a ghost disturbance, however, the waveform equalizer
203
calculates, with respect to the data, an error between the data and the value of +7, and calculates an incorrect filter coefficient on the basis of the error.
Similarly, consider a case where the loop gain of the clock regenerating circuit is set to a large value.
In this case, the speed of clock regeneration processing following a feedback signal is increased, so that the loop gain of the clock regenerating circuit converges at high speed. When a ghost disturbance exists in the received signal in this case, however, the clock regeneration processing sensibly responds to a ghost component (the clock frequency is liable to vary). Accordingly, jitter occurs in a regenerated clock in the VSB receiver, so that an error occurs in the received signal.
Then, consider a case where the loop gains of the AGC circuit and the clock regenerating circuit are respectively set to small values.
In this case, in the AGC circuit, the speed of AGC processing fol
Azakami Hiroshi
Konishi Takaaki
Ueda Kazuya
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