Semiconductor device manufacturing: process – With measuring or testing – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2001-07-24
2003-06-17
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
With measuring or testing
Packaging or treatment of packaged semiconductor
C438S014000, C438S017000, C438S612000, C438S617000, C257S779000
Reexamination Certificate
active
06579734
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a bonding pad (electrode) which is one part of an integrated circuit.
2. Description of Related Art
Technology that is related to the present invention will be briefly described with reference to FIGS.
6
(A) through
6
(D). Following the completion of the wafer process and prior to wire bonding, a probe test (also called a wafer test) is performed in order to ascertain the acceptability of the product as a semiconductor element. In this probe test, as is shown in FIG.
6
(A), a probe needle
24
is caused to contact a bonding pad (electrode)
12
on the surface of he semiconductor wafer, and electrical characteristics are tested. For example, as is shown in FIG.
6
(A), this bonding pad
12
is formed on the surface of an inter-layer insulating film
10
such as a silicon oxide film with a TiN film
16
and Ti film
14
interposed, and the region that is to be wire-bonded on the pad surface is demarcated by a Ti film
18
, a TiN film
20
and a passivation film
22
, etc.
In cases where the semiconductor element is judged to be defective on the basis of the results of this probe test, treatments such as trimming of the internal voltage corresponding to the semiconductor chip or redundant replacement of the faulty bits, etc., are performed prior to wires bonding.
These treatments are accomplished by utilizing a laser beam, etc., to blow away (evaporate) desired fuses among the fuses installed inside the semiconductor chip, together with the passivation films formed on these fuses, so that these fuses are cut.
Furthermore, in the case of LSI circuits with multi-layer wiring (or interconnection), the fuses are installed in a metal layer which is formed on top of the uppermost polysilicon layer among several polysilicon layers. Moreover, the fuses installed in this metal layer will be referred to below as “metal fuses”. Metal layers equipped with such metal fuses ordinarily consist of aluminum (Al).
Accordingly, in the case of semiconductor wafers equipped with such metal fuses, a protective film
28
such as a passivation film (insulating film), etc., is again formed over the entire surface of the wafer as shown in FIG.
6
(B) following the cutting of the metal fuses, so that contact between the cut surfaces of the fuses and the water content that is absorbed in the package is avoided, thus preventing corrosion of the Al layer.
Since this protective film is formed, the bonding pad
12
that has been probe-tested is covered by this protective film
28
as shown in FIG.
6
(C). Accordingly, the bonding pad
12
is exposed by etching the protective film
28
.
However, the bonding pad is damaged by needle tracks, etc., as a result of contact with the probe needle during the probe test (indicated by
26
in FIGS.
6
(A) and
6
(B). Since the damaged region of the bonding pad is etched when the protective film is re-etched, a hole
31
which exposes the underlying layer
14
is formed in this damaged region, or a deep recess is formed.
Conventionally, the regions where the probe test and wire bonding are performed on the abovementioned bonding pad are substantially the same region.
Accordingly, the contact area between the bonding pad
12
and the wire
32
is reduced, so that favorable wire bonding cannot be obtained. Furthermore, wire bonding becomes difficult.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a bonding pad with a structure that allows favorable bonding of a wire to an undamaged region of the bonding pad even if the bonding pad is damaged by a probe test.
A second object of the present invention is to provide a semiconductor device which is equipped with the above-mentioned bonding pad.
A third object of the present invention is to provide a method for performing wire bonding on the above-mentioned bonding pad.
The semiconductor element bonding pad of the present invention has a wire bonding region and a test region which is separated from the wire bonding region.
As a result of such a bonding pad structure, the bonding pad can be set with a wire bonding region that is required for joining with the wire in the case of wire bonding, and a test region required for characteristic tests, etc., performed on the semiconductor element, and both of these regions can be set as respectively different regions.
Accordingly, in the case of wire bonding, the wire can be joined to the wire bonding region so that joining of the wire to the damaged test region on the bonding pad can be avoided. Consequently, wire bonding can be performed easily and reliably.
As a result, a semiconductor device with good wire bonding characteristics can be obtained.
REFERENCES:
patent: 5517127 (1996-05-01), Bergeron et al.
patent: 5981370 (1999-11-01), Rincon et al.
patent: 6166556 (2000-12-01), Wang et al.
patent: 6251694 (2001-06-01), Liu et al.
patent: 6297561 (2001-10-01), Liu et al.
patent: 2002/0016070 (2002-02-01), Friese
Oki Electric Industry Co. Ltd.
Pham Long
Rabin & Berdo PC
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