Electric power conversion systems – Current conversion – Including d.c.-a.c.-d.c. converter
Reexamination Certificate
2001-08-17
2003-06-24
Sterrett, Jeffrey (Department: 2838)
Electric power conversion systems
Current conversion
Including d.c.-a.c.-d.c. converter
C363S127000
Reexamination Certificate
active
06583993
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a logic integrated circuit. In particular, the present invention relates to a self-driven, synchronous rectification scheme for a power converter which is easily adapted to various circuit topologies.
There is an ever-increasing demand in the power electronics market for low voltage and high current DC—DC converters. As output voltage is desired to be 3.3V or lower, even a state-of-the-art schottky diode with a forward voltage drop of 0.3V has an unacceptable amount of power loss.
Because of this, synchronous rectifiers are often used to improve the efficiency of DC—DC converters. Generally, there are two types of synchronous rectifiers, self-driven and externally driven. Since the self-driven mode is usually less complex, less costly and more reliable, it is preferred for use with most low voltage DC—DC converter applications.
FIG. 1A
illustrates a conventional self-driven synchronous rectification, asymmetrical, zero voltage switching (ZVS) half-bridge (HB) topology. Although this circuit is very simple, it is only suitable for applications where the output voltage is in the range of from about 3.3V to 6V. Referring to
FIG. 1B
, the gate-drive voltages V
gs3
and V
gs4
of synchronous rectifiers S
3
and S
4
, respectively, are as follows:
V
gs3
=
2
N
s
N
p
DV
in
=
2
N
DV
in
=
V
0
1
-
D
(
t
0
≤
t
≤
t
1
)
(
1
)
V
gs4
=
2
N
s
N
p
(
1
-
D
)
V
in
=
2
(
1
-
D
)
N
V
in
=
V
0
D
(
t
1
≤
t
≤
t
2
)
(
2
)
wherein, V
in
is the input voltage; V
o
is the output voltage; D is the steady-state duty cycle; N
p
is the number of primary winding turns of the transformer; N
s
is the number of secondary turns of the transformer; and N is the turns ratio of the transformer. The turns ratio of the transformer TR is calculated by dividing the number of primary windings by the number of secondary windings (i.e. N=N
p
/N
s
).
FIG. 1B
illustrates the switching waveform occurring in the converter illustrated in FIG.
1
A. As shown in
FIG. 1B
, the gate-drive voltage V
gs4
of S
4
is always higher than the gate-drive voltage V
gs3
of S
3
if D is less than 50%. If we assume that the minimum steady-state duty cycle D at heavy load is 30%, then V
gs3
is about 1.4V, and V
gs4
is about 3.3V. Since most synchronous rectifiers (including logic level devices) only work well with the gate-drive voltage between about 4V and 20V, the circuit shown in
FIG. 1A
only works well when the output voltage V
O
is between 2.9V to 6V. If the output voltage is below 2.9V, S
3
would be under driven. If the output voltage were about 6V, then S
4
would be over driven. In either case the synchronous rectifiers are easily rendered inoperative.
Accordingly, there remains a need for a self-driven synchronous rectifier which operates normally at various output voltages, such as low output voltages of 2.9V or lower and/or high output voltages above 6V.
SUMMARY OF THE INVENTION
The self-driven synchronous rectification circuit of the present invention includes two power switches S
1
and S
2
; a transformer Tr having a primary winding with N
p
number of turns, a secondary winding with N
s
number of turns and an auxiliary winding with N
a
number of turns; two secondary synchronous rectifiers S
3
and S
4
; two diodes D
1
and D
2
; and two zener diodes ZD
1
and ZD
2
.
The number of auxiliary winding turns N
a
of the transformer Tr ensure that the synchronous rectifiers S
3
and S
4
are supplied with an adequate gate-drive voltage. The selection of the number of auxiliary winding turns for use is determined according to the output voltage required. In the circuit of the present invention, when S
3
conducts, the gate-drive voltage of S
4
is clamped by D
1
. Also, when S
4
conducts, the gate-drive voltage of S
3
is clamped by D
2
. In other words, D
1
and D
2
prevent S
3
and S
4
from conducting at the same time. ZD
1
and ZD
2
restrain the gate overvoltage of S
3
and S
4
, respectively.
With the above circuit configuration, a self-driven synchronous rectification scheme can be implemented which operates normally at various output voltages, such as low output voltages of 2.9V or lower and/or high output voltages above 6V.
REFERENCES:
patent: 4519024 (1985-05-01), Federico et al.
patent: 4716514 (1987-12-01), Patel
patent: 5038266 (1991-08-01), Callen et al.
patent: 5274543 (1993-12-01), Loftus
patent: 5663877 (1997-09-01), Dittli et al.
patent: 5734563 (1998-03-01), Shinada
patent: 6011703 (2000-01-01), Boylan et al.
patent: 6104623 (2000-08-01), Rozman
patent: 6169675 (2001-01-01), Shimamori et al.
patent: 6275401 (2001-08-01), Xia
patent: 6301139 (2001-10-01), Patel
Bel Fuse Inc.
Ostrolenk Faber Gerb & Soffen, LLP
Sterrett Jeffrey
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