Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2000-03-09
2003-11-11
Ngo, Chuong Dinh (Department: 2787)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S710000
Reexamination Certificate
active
06647405
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an adder circuit, an integrating circuit which uses the adder circuit, and a synchronism detection circuit which uses the integrating circuit. In particular, the present invention pertains to an adder circuit, an integrating circuit using such an adder circuit, and a synchronism detection circuit using such an integrating circuit, which can perform addition or integral calculations or can establish synchronism.
2. Related Arts
In order to cope with the increased number of digital portable telephones users, the CDMA (Code Division Multiple Access) system, which can allocate more channels to limited frequencies, has been proposed as a communication system. The CDMA system adds a diffusion code consisting of a plurality of bits to transmission data in order to allocate, for a single frequency, the number of channels which corresponds to the number of types of diffusion codes. A common diffusion code, established between a transmission side and a reception side, is employed by the transmission side to modulate data to be transmitted, while the reception side employs the diffusion code to demodulate the received data.
In this case, the reception side must establish synchronism to detect the timing for allocation of the diffusion code. Generally, synchronism is established by using a matched filter. That is, inverse diffusion is effected by performing integral damping, using a diffusion code, for a received signal which is diffused by the diffusion code. The timing at which an integral value reaches a predetermined peak value is detected as synchronous timing. Therefore, the matched filter must perform integral calculations.
However, a conventional integrating circuit has flip-flops at the front and at the rear stages of an adder circuit for temporarily latching input bits and output bits. In synchronism with a predetermined clock, the integrating circuit repeats an addition sequence by which addend data are added to integral augend data, and latches newly obtained data at the flip-flop at the rear stage. In other words, basically the integrating circuit performs integral calculations by repeating the addition sequence each clock cycle. For this reason, clock cycle timing must be so set that the length of each cycle corresponds to the length of the addition sequence that will take the longest time to perform. As a result, even when a specific addition sequence is completed early, the integrating circuit can not immediately begin the next addition sequence, but must wait for the next clock.
When a matched filter using the above integrating circuit is employed for a portable telephone, the frequency of an operating clock can not be increased because of the need to save power, due to an inherent requirement for a portable telephone. Therefore, even if an adder can perform an operation quickly, or even if a data addition sequence should be completed in as short a time as possible, since the frequency of the operating clock is low, the time needed to perform an integral calculation for which a number of addition sequences are required can not be shortened.
SUMMARY OF THE INVENTION
It is, therefore, one objective of the present invention to provide an integrating circuit for which the integral calculation time can be shortened without depending on clock speed.
It is another objective of the present invention to provide a synchronism detection circuit which can establish synchronism in a shorter time without depending on clock cycles.
To achieve the above objectives, according to the present invention, an adder circuit, which receives addend data and augend data, each of which consists of a plurality of bits, and sums said addend and augend data, comprises:
a plurality of adder blocks, for adding a predetermined number of bits of said addend data to a like number of bits of said augend data, and for outputting both the addition result having said predetermined number of bits and a carry-out signal,
wherein, each adder blocks generates a block addition end signal which indicates that the addition performed by said adder block has been completed, in response to a carry-out thereof, when the carry-out occurs, in accordance with a set of a carry-out signal from a lower adder block, said addend data and said augend data; and
not in response to the carry-out thereof, when the carry-out does not occur in accordance with said set.
According to the present invention, block addition end signals are received from the plurality of adder blocks, and in response to the timing at which all the block addition end signals indicate addition was completed, an addition end signal for the adder circuit is generated.
Further, according to the present invention, in response to a block addition end signal from the highest adder block, the addition end signal for the adder circuit is generated.
Furthermore, according to the adder circuit above, since a block addition end signal indicating a calculation has been completed is generated by all the adder blocks, the timing at which addition is completed, being different depending on the addend data and augend data set, can be detected.
In addition, to achieve the above objectives, according to the present invention, an integrating circuit comprises:
an adder circuit as described above;
an addend data input buffer for recording addend data; and
an addition result buffer for recording the results of addition and for outputting addend data,
wherein, in response to the addition end signal, the addend data and the augend data are supplied from the addition data input buffer and the addition result buffer to the plurality of adder blocks.
Since the integrating circuit of the present invention performs a plurality of additions by itself, the integral calculation time can be reduced.
Furthermore, to achieve the above objectives, according to the present invention, A synchronism detection circuit, which detects the synchronism of diffusion code for a received signal subject to a code diffusion, comprises:
an integrating circuit as described above;
a plurality of delay circuits, each of which delays said received signal having a plurality of bits; and
a plurality of multiplication circuits for multiplying by the outputs of said plurality of delay circuits and the diffusion code having a plurality of bits respectively,
wherein the outputs of said multiplication circuits are accumulated by said integrating circuit, and said synchronism is detected according to the accumulation result.
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M. W. Allam et al., Low Power Implementation of Fast Addition Algorithms, 1998, IEEE, p. 645-647.*
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Hikita Mahiro
Kanasugi Masami
Kuroiwa Koichi
Taniguchi Shoji
Arent Fox Kintner & Plotkin & Kahn, PLLC.
Do Chat
Ngo Chuong Dinh
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