1996-09-26
1999-02-23
Beausoliel, Jr., Robert W.
39518212, 39575004, G06F 1100
Patent
active
058753486
ABSTRACT:
Disclosed is a computer system that includes a CPU that can be operated both in a normal mode and in a power saving mode. The system further includes at least one peripheral device and a bus for allowing communication between the CPU and the peripheral device. A bus cycle detector monitors a bus cycle on the bus and a condition determiner determines the operation mode for the CPU in a specific bus cycle that is detected by the bus cycle detector. A signal generator is used to provide to the CPU, a control signal for changing the CPU's operation mode in accordance with a determination result obtained by the condition determiner. The disclosed system can reduce the operating frequency of a CPU or halt the operation of the CPU in accordance with an appropriate timing even when asynchronous communication is performed with peripheral devices.
REFERENCES:
patent: 5293494 (1994-03-01), Saito et al.
patent: 5423045 (1995-06-01), Krishnamurthi et al.
patent: 5548766 (1996-08-01), Kaneko et al.
patent: 5623677 (1997-04-01), Townsley et al.
Kawano Saiichi
Matsushima Shinji
Nakano Masayoshi
Shiraishi Yuichi
Beausoliel, Jr. Robert W.
Elisca Pierre Eddy
International Business Machines - Corporation
Magistrale Anthony N.
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